Restore ZedBoard factory booting

[mvernengo]

I have been working with ZedBoard for one year by now, but always on the "PL" (FPGA) side. I managed to test many  FPGA designs with Vivado 2022.2 without any problem. However when I tried to program the PS side, I did something wrong and now, when I power ZB off and on, the system is not booting with the factory setting anymore. Hence the DIGILENT brand is no longer shown at the OLED display and the blue "done" LED is not lighting up anymore.

---> What I want is to restore the ZB to the original factory setting booting.

---> So that the DIGILENT brand is displayed again at the OLED.

 

In case somebody can help me, I explain below in detail what happened. However, I want to state in advance of below description that I later managed to recover some kind of communication with ZB by changing the settings of the JP7 to JP11 jumpers the "JTAG mode", but the problem is that now I don't know what commands to use with xsct and JTAG-USB connector in order to recover the original configuration booting.

 

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DETAILED DESCRIPTION OF THE PROBLEM:

Some 10 days ago I made my first application for communication between PS (dual core ARM Cortex-A9) and PL with Vitis 2022.2. But when I tried my second application of this type, I did something wrong and lost the communication with Zedboard, either through Vivado or Vitis. This means that Vivado stppped detecting ZB as target and with Vitis, the xsct "target" command could not detect any target giving the message:

xsct% targets
  2  whole scan chain (DR shift output all ones)

(The above result was obtained connecting my notebook serial port to the USB-JTAG port used for programming).

Fortunately, as I have another ZB at the university I work, I can know what would be the expected "factory setting" result which is the following:

xsct% targets
  1  APU
     2  ARM Cortex-A9 MPCore #0 (Running)
     3  ARM Cortex-A9 MPCore #1 (Running)
  4  xc7z020
 

Additionally, when connecting my notebook serial port to the UART-USB port of ZB, I keep receiving a permanent transmission of a strange ASCII character like in the following image:

Interestingly, when I press the PS-RST red button at ZB, the terminal stops receiving this weird ASCII character, but reception is automatically resumed when the PS-RST button is released.

Hence, my assumption is that I did something wrong when programming the ZB with Vitis, and for some reason, the ARM CPU got caught in an infinite loop that sends an ASCII character continuosly, and it can no longer execute any normal booting. As a matter of fact, the C program I had tried to implement actually is supposed to send an ASCII text continuosuly inside a loop, (although not the same character all the time but different ones depending on what the FPGA side detects).

Also, when I tried to access to the PL side through Vivado, the "Open Target" command at the GUI could NOT manage to detect my "faulty ZB" and of course this means I no longer was able to program any "LED blinking" hardware to test if the xc7z020 SoC was "still alive".

All of this happened with the JP7 to JP11 jumpers set to factory status:

I then looked into the "ZedBoard Configuration and Booting Guide" and saw that there is a "JTAG booting mode":

After setting the faulty ZB jumpers to the "JTAG booting Mode", I managed to obtain the same response as with the "non faulty ZB":

xsct% connect
tcfchan#1
xsct% targets
  6  APU
     7  ARM Cortex-A9 MPCore #0 (Running)
     8  ARM Cortex-A9 MPCore #1 (Running)
  9  xc7z020

Moreover, with this jumper setting, I recovered the connection to the "Faulty ZB" with Vivado on the PL-side and managed to program a "LED blinking" hardware-test configuration without problem.

 

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CONCLUSIONS:

I did something wrong with Vitis and programed the PS-side into some kind of "baremetal application with an infinite loop" that does not allow the "faulty ZB" to communicate with any notebook application that connects through the JTAG-USB (PROG) connector in case the JP7 to JP11 are configure to factory settings. But when I change the jumper settings to "JTAG booting mode" I recover the communication through the JTAG-USB interface, being able to send xsct commands and program the PL again. But what I want is to simply return the "faulty ZB" ti the original factory state, meaning that with the normal factory setting of the ZB I can also program the de PL side and connect using xsct commands and more important that the booting process has the result of showing the DIGILENT brand in the OLED display.

 

Any help or comment will be deeply appreciated. Thanks in advance.

 

[JColvin]

Hi @mvernengo,

What revision of the Zedboard do you have? Neither the Rev D nor the Rev F of the Zedboard that I have match the silkscreen image you posted with the Mode numbering (my two versions list the MIO numbers), though the jumper numbering (JP7..11) does match. My concern is that if the jumper numbering is identical that then the Mode[X] silkscreen labels would not readily line up with the orientation listed in Table 18 of the Zedboard User Guide that Avnet created here: https://digilent.com/reference/_media/reference/programmable-logic/zedboard/zedboard_ug.pdf.

Presuming the latter situation, your setup of Mode3 and Mode2 being set high would have the device boot from Quad SPI flash memory (which is based on Mode2 high, and both Mode1 and Mode0 low), which from my understanding is not loaded or prepared by default with the Out-Of-Box material. That would be loaded through the SD card image (Boot Modes 2 and 1 set to logic high), which you can find in the Zedboard Resource Center here: https://digilent.com/reference/programmable-logic/zedboard/start#additional_resources.

I would also put Mode3 to logic low to set the device to Cascaded JTAG rather than Independent JTAG so that you can more readily access the device as per Table 22 in above linked user guide.

As for the serial terminal not responding in readable characters, my gut reaction would be to double check the baud rate (by default Zynq designs use 115200 baud, but Tera Term uses 9600 baud by default).

Let me know what you find out.

Thanks,
JColvin

[mvernengo]

Hi, JColvin, thanks for your kind response.

 

1) The image of jumpers was not from my board (sorry for not clarifying that), it was from AVNET booting guide. This one in below image is of my ZB (now set with "JTAG booting mode"):

 

2) As the jumper names changed from AVNET booting guide and my ZB (MODEx --> MI 0x) I assumed the jumper number is the one to be respected. Hence, I can tell you that all the boards that my university purchased come with the following factory setting:

JP7 = MI 02 (= MODE0) ---> GND.

JP8 = MI 03 (= MODE1) ---> GND.

JP9 = MI 04 (= MODE2) ---> 3V3.

JP10 = MI 05 (= MODE3) ---> 3V3.

JP11 = MI 06 (= MODE4) ---> GND.

 

3) I will carefully read the documentation you sent me, but for your reference at this moment my understanding about ZB booting process is almost null.

What I can tell you is that:

- Until 2 weeks ago I had just used Vivado ( = PL/FPGA programming) with the factory setting as in 2) above and the booting consisted simply in (a) power LED ON, (b) "done" LED ON, (c) OLED displaying the "DIGILENT" logo.

- Whenever I powered OFF the ZB, the FPGA programming was lost and the booting was exactly the same as before mentiones (which I assumed was normal unless I changed to some kind of "baremetal" application).

- I started using Vitis first time just 10 days ago and followed a tutorial on the web, managing to program a "NAND application" with "AND in the PL and NOT in the PS". The app communicated through serial port without problems to send some hello world message. I also modified it so that it sent an incremental counter of the PS-side through the console every time the NAND output was = 1, stopping the transmission if the NAND output = 0. Hence there is no issue with baud rate at all, I am sure.

- Then, I tried to program a more "complicated" (not really) application with (a) information sent from the PS to the PL, (b) the PL doing some data processing (c) the PL sending back the result to the PS  and (d) the PS showing the result of the processing in the console. But "something went wrong", it never worked but when I powered OFF/ON the ZB, the "done LED" never lit up again and the OLED displayed remained dark for eternity. I had only power ON LED.

- Additionally, the communication was completely lost with ZB, either through the UART-USB or the PROG/JTAG-USB (XSCT). Of course, as PROG interface stopped working, I could neither program the FPGA.

- Finally, I found the AVNET booting guide and tried the jumper cofigurations with JP7 to JP11 all to GND ("JTAG booting mode") and I "magically" recovered the communication with ZB through the PROG/JTAG/XSCT USB (again, no baud rate issue I am sure), and I am also being able to program the FPGA side again, but the booting process has not changed: "done" LED never goes ON (except if I program the FPGA, which is now possible) and the OLED display is still not showing "DIGILENT" logo.

- I also tried to program with Vitis the app that had originally worked (the incrementing counter) but it is not working anymore. It shows garbage in the console (the FPGA side of this app does work, a LED lights depending on the result of the NAND). But I am sure the baud rate is correct on the PC side because I am still able to communicate and send commands with XSCT, which works with the same baud and other communications settings.

- Anyway the important part for me is that the booting process has not returned to normal.

 

Hence, I will keep waiting for additional ideas that you may figure out after my above comments. And meanwhile I will read the documentation that you sent. In case that I have some questions after reading it, I will be grateful if you could continue kindly answering.

 

Thanks again for your help and regards,

 

Martin (mvernengo).

 

On 1/2/2024 at 9:22 PM, JColvin said:

Hi @mvernengo,

What revision of the Zedboard do you have? Neither the Rev D nor the Rev F of the Zedboard that I have match the silkscreen image you posted with the Mode numbering (my two versions list the MIO numbers), though the jumper numbering (JP7..11) does match. My concern is that if the jumper numbering is identical that then the Mode[X] silkscreen labels would not readily line up with the orientation listed in Table 18 of the Zedboard User Guide that Avnet created here: https://digilent.com/reference/_media/reference/programmable-logic/zedboard/zedboard_ug.pdf.

Presuming the latter situation, your setup of Mode3 and Mode2 being set high would have the device boot from Quad SPI flash memory (which is based on Mode2 high, and both Mode1 and Mode0 low), which from my understanding is not loaded or prepared by default with the Out-Of-Box material. That would be loaded through the SD card image (Boot Modes 2 and 1 set to logic high), which you can find in the Zedboard Resource Center here: https://digilent.com/reference/programmable-logic/zedboard/start#additional_resources.

I would also put Mode3 to logic low to set the device to Cascaded JTAG rather than Independent JTAG so that you can more readily access the device as per Table 22 in above linked user guide.

As for the serial terminal not responding in readable characters, my gut reaction would be to double check the baud rate (by default Zynq designs use 115200 baud, but Tera Term uses 9600 baud by default).

Let me know what you find out.

Thanks,
JColvin

 

[mvernengo]

Sorry, I forgot answering about the board revision.

I can read PB200-24B Rev. F near the serial number DB1888A.