WaveForms Logic Analyzer: can't find a way to filter glitches?

[Alrie]

Hello everybody,

i'm sporting an AD Pro 3450 and looking for a way to filter for glitches in the waveforms logic analyzer, similar to the ones circled in red here:

I'm getting these on one of my SPI lines and the noise is messing with the logic analyzer function. As you can see, some bytes are not interpreted correctly due to the spikes, so i'm looking for a glitch filter function that goes "ignore all pulses shorter than n nanoseconds". As this seems like a fairly straight forward thing, sorry if i'm being stupid and can't find it (i've spent time googling, i swear 😁)

Obligatory; i tried fixing the issue in hardware, but wasn't successful, despite rerouting the probe cable and changing some pin settings of the SPI master. Putting an Analog Probe on that line doesn't show any substantial noise, so it looks like the problem originates in the scope and there might be crosstalk in the frontend of the digital inputs.

If waveforms doesn't have a simple glitch filter function like what i'm looking for, i'd ask if there is either some other function to achieve the same thing (i.e. adjust the threshold voltage between logic high and logic low) or some sort of automation interface in waveforms that i could use (i.e. custom protocol scripting, or custom filter scripting or similar).

I'd appreciate any help! And wish all of you a good start into the new year :)

Edited December 30, 2023 by Alrie

[JColvin]

Hi @Alrie,

I'm not certain what you might have as a triggering setup, but presuming that these Chip Select glitches aren't the software unintentionally toggling the CS line and using something like a weak pulldown resistor doesn't work in your situation, you can use the Pulse/Timeout to have it only trigger low CS negative pulses that exceed some length of time:

Let me know if that works for you (or if it doesn't quite work for your system so we can troubleshoot further).

Thanks,
JColvin

[attila]

Hi @Alrie

To reduce crosstalk between wires try twisting each signal wire with GND or at least the critical ones like CS and CLK

Make sure the digital IO voltage is set correctly since this also adjust the input logic threshold (about half of the VIO)