PmodUSBUART does not work in Kintex7_1G_CML NetFPGA

[tuan_gcs]

Dear all

I build a system EDK using option  "Create a System for a Customer board" on   Kintex7_1G_CML, as setup UART connection in system.ucf

I found two documents that describes

Follows the Digilent Pmod Interface Specification Type 4 : TXD connect to Pin 2, and RXD connects to pin 3  

Follows to https://reference.digilentinc.com/reference/pmod/pmodusbuart/reference-manual:  Pin 2 to RXD and Pin 3 to TXD 

However even i swap two pins together, but UART still does work, no line "Hello" displays on Terminator PC

Any help, advise

Thank so much

Tuan Trong

 

[jpeyron]

Hi Tuan Trong,

Were you able to complete the manufacturing test from the reference manual here under Appendix A which uses the PmodUSBUART?

cheers,

Jon 

[JColvin]

Hi Tuan,

I have asked some of our applications engineers about this; they will get back to you here on the Forum.

As a clarification though (I'll update the reference manual to make this more clear) the RXD and TXD are from the perspective of the embedded FTDI chip on the PmodUSBUART. So, Pin 2 (RXD) is data flowing from the host to the Pmod, and Pin 3 (TXD) is data flowing from the Pmod to the host.

Thanks,
JColvin

[tuan_gcs]

6 hours ago, jpeyron said:

Hi Tuan Trong,

Were you able to complete the manufacturing test from the reference manual here under Appendix A which uses the PmodUSBUART?

cheers,

Jon 

Dear Jon,

I did not found any reference manufacturing testing on Digilentic website

Thanks 

Tuan,

 

[tuan_gcs]

6 hours ago, JColvin said:

Hi Tuan,

I have asked some of our applications engineers about this; they will get back to you here on the Forum.

As a clarification though (I'll update the reference manual to make this more clear) the RXD and TXD are from the perspective of the embedded FTDI chip on the PmodUSBUART. So, Pin 2 (RXD) is data flowing from the host to the Pmod, and Pin 3 (TXD) is data flowing from the Pmod to the host.

Thanks,
JColvin

Dear Mr. Jcovin

UART does not work even I had swap two pins in system.ucf

NET axi_uartlite_0_RX_pin         LOC = H18 | IOSTANDARD = LVCMOS33;
NET axi_uartlite_0_TX_pin         LOC = E15 | IOSTANDARD = LVCMOS33;

or 

NET axi_uartlite_0_RX_pin         LOC = E15 | IOSTANDARD = LVCMOS33;
NET axi_uartlite_0_TX_pin         LOC = H18 | IOSTANDARD = LVCMOS33;

Would you like ask your applications engineers support the bsp file (board support package) that embedded on EDK  

Please give me your advise

Best regards

 

Tuan Trong

[tuan_gcs]

Dear Mr.JColvin

Attached file is system.ucf  nad system.mhs please have looking inside and find out my errors/problems

Also, would you like give me your email, so that i can send the EDK project for your consideration ?

Thanks

Tuan Trong

 

system.mhs

system.ucf

[jpeyron]

Hi Tuan Trong,

I did a little digging and i found the manufacturing testing here. Hopefully this will  help!

cheers,

Jon 

[jpeyron]

Hi Tuan Trong,

I'd suggest to use the registration link on the Getting started page at:  https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-1G-CML-Getting-Started-Guide.

Your access might take up to 5 days to be granted but then you will get more experienced support for the Kintex7_1G_CML from NetFPGA forum. 

cheers,

Jon