3 questions about zybo z7 schematic

[jowell88]

Hi,

I'm designing a board based on the zynq z7010. I have few questions about the zybo z7 schematic (rev d1).

1 : A FTDI FT2232HQ is mentionned in the reference manual but I can't find it in the schematic. It has been removed ? Why ?

2 : At sheet 13 pin VREFCA and VREFDQ of DDR require bypass capacitor but why C177 (CA Byp) is connected to VCC1V35 since the reference voltage is DDR3_VREF for both pin ?

3 : MIO bank 0  is set to 3V3 VMODE (MIO7 pin pulled down to GND with 20k > UG933 table 5-3) and MIO bank 1 is set to 1V8 VMODE, but UG933 says "If the MIO bank voltage is incorrectly set, the I/O behaves unpredictably and damage might occur. An exception to this requirement are temporary Boundary Scan EXTEST operations which require 1.8V MIO banks to use a 2.5/3.3V VMODE setting for correct EXTEST operation". Since MIO bank 1 is set to 1V8 mode, the EXTEST operation won't work correctly on zybo z7 ?

[JColvin]

Hi @jowell88,

1. Digilent has made the choice not to provide the details about the implementation of this in our boards. You can read more about it some other threads such as these two: https://forum.digilent.com/topic/20362-usb-proguart-schematic-request/, https://forum.digilent.com/topic/27253-schematic-for-original-arty-missing-usb-connector-and-ftdi-chip/.

I will get clarification on questions 2 and 3 to make sure I'm not providing misinformation.

Thanks,
JColvin

[JColvin]

Hi @jowell88,

I apologize for the delay regarding on questions 2 and 3; this is the clarification that I have received.

Quote

At sheet 13 pin VREFCA and VREFDQ of DDR require bypass capacitor but why C177 (CA Byp) is connected to VCC1V35 since the reference voltage is DDR3_VREF for both pin ?

C177 and C178 are both present because VrefCA and VrefDQ as per the Micron datasheet (https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_1_35v_ddr3l.pdf) on Table 22 expect to have voltages of Vdd/2.

DDR3_Vref sources this from a voltage divider (middle of page 10 of the Zybo Z7 schematic), and then the combination of C177 & C179 and C178 and C180 provide further stabilization of this voltage as required by Table 21 and Table 22 of the Micron datasheet. Addtionally, VrefCA and VrefDQ should track any variations on Vcc1V35. So the two equal-value capacitor pairs will represent relatively small impedances for short-term variations from Vcc1V35, effectively forming voltage dividers that cause short-term variations on Vcc1V35 to be tracked by both Vref inputs.

Quote

MIO bank 0  is set to 3V3 VMODE (MIO7 pin pulled down to GND with 20k > UG933 table 5-3) and MIO bank 1 is set to 1V8 VMODE, but UG933 says "If the MIO bank voltage is incorrectly set, the I/O behaves unpredictably and damage might occur. An exception to this requirement are temporary Boundary Scan EXTEST operations which require 1.8V MIO banks to use a 2.5/3.3V VMODE setting for correct EXTEST operation". Since MIO bank 1 is set to 1V8 mode, the EXTEST operation won't work correctly on zybo z7 ?

You are correct that the EXTEST operation will not work on the Zybo Z7 as per the note Table 5-3 in UG933 and the corresponding answer record (https://support.xilinx.com/s/article/57930?language=en_US). There is no way to temporarily change the bank voltage on MIO1/Bank 501 from 1.8 V to any other value on the Zybo Z7.

Let me know if you have any questions.

Thanks,
JColvin