Not enough BRAM on Nexys AT 100 T

[Lusohlba]

Hello everyone,

I would like to implement an independent clock BRAM FIFO using the IP FIFO generator. The maximum wirte depth with which I can generate the bit stream is 4096 (with a wirte width of 96). Is it possible to make changes in the settings so that more BRAM is available? How much BRAM would theoretically be available? Thank you in advance for your help!

Best,

Lukas

Edited November 8, 2023 by Lusohlba

[zygot]

In practical terms, there are only so many BRAMs that one can combine to create a large memory that meets timing reliably at a reasonable data rate. If your needs are for an asymmetric memory, that is different ports widths then this complicates things. If you are creating a true DPRAM with read/write ports using a different clock, then this also complicates the design.

I suppose that if you use really low frequency clocks, or have many clock periods between read and write operations, then you might be able to bypass the guard rails of the vendor IP and create a memory using HDL without the IP. FPGA vendor documentation describes HDL syntax that the tools will infer various types or memory structure from. There's no harm in doing some experimentation to see what results you get.

You'd probably agree that a memory that seems to work some of the time isn't very useful, so extra effort in verification is required when you bend the rules.

In theory, one could use 100% of the BRAM of a device for one giant memory. In practice, this might not be a good idea.

If your application needs a really large amount of storage, there's always the external DDR memory. Edited November 8, 2023 by zygot

[zygot]

Terasic has a PCIe demo for it's C5P Cyclone IV and Cyclone V boards that implement 512 KB memories, which is a substantial percentage of the total BRAM for those devices. They are the slowest speed grade devices. So, it depends on the device, the device speed grade, and perhaps the tool version.

For the Artix 200T in the Nexys Video I've implemented 128 KB storage elements like DPRAMs and FIFOs. For the speedier Kintex on the Genesy2 I've implemented 256 KB storage elements. I've done this using Vivado IP. This doesn't represent a hard limit, just a boundary that the tools set at a limit. Can you instantiate multiple 128 Kb FIFOs on your board? Perhaps. Can you make timing for the complete design? I can't venture a guess about that.

Usually, there are design approaches for achieving performance that a simple straight-forward approach doesn't allow. If one way doesn't work, consider an alternate design approach. Edited November 8, 2023 by zygot