Lusohlba

Hello everyone, I would like to implement an independent clock BRAM FIFO using the IP FIFO generator. The maximum wirte depth with which I can generate the bit stream is 4096 (with a wirte width of 96). Is it possible to make changes in the settings so that more BRAM is available? How much BRAM would theoretically be available? Thank you in advance for your help! Best, Lukas

Hello everyone, I would like to use the microSD solot on the Nexys A7 100T to implement a data logger for the FPGA. Can someone tell me what kind of SD card I need for this or which cards are supported? SD 1.0, 2.0....? Or does it depend on the sd card controller implemented on the FPGA? Has anyone by chance already implemented a data logger for the Nexys A7 100T? Thanks in advance for the support. Best, Lukas