I need help with locating the mig.prj file for the artyz7-10 fpga board.

[Yatharth Gupta]

Hi all,

For an ongoing project I need the mig.prj file for the diligent arty-z7-10 board. On referring the following link I could not find the same under the required folder.

https://github.com/Digilent/vivado-boards

Is there any common file that can be used for the same?

 

Thank you for your time.

Regards,

Yatharth Gupta

[JColvin]

Hi @Yatharth Gupta,

DDR memory on Zynq based boards are connected directly to the PS, so you do not use a mig.prj like you would for a non-Zynq 7-series board.

Presuming you have the Digilent Board Files installed (either via this method, https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files, or by installing them via the Xilinx Board Store when initially choosing a part upon creating a project), after you add the Zynq processor to your block design, run block automation and leave the Apply Board Preset checked, and the DDR memory will be connected for you; https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi#add_a_processor_to_a_block_design.

Let me know if you have any questions or if I am misunderstood what you are wanting to do.

Thanks,
JColvin

[Yatharth Gupta]

Hey JColvin,

Thank you for your reply. 

I'm currently working on migrating an open-source RISC-V SoC project from the Arty A7-100T board to the Arty Z7-10 board. However, I've hit a roadblock in the process. I need a mig.prj file tailored to the Arty Z7-10 board, to work with the tool chain. 

I'm currently facing difficulty when it comes to assigning register bank 504 to the DDR3 memory within the Memory Interface Generator IP block.

Could you provide me with guidance on detailed process or an alternative approach for generating the 'mig.prj' file specific to the Arty Z7 board?

Thanks and regards,

Yatharth Gupta

 

Edited November 3, 2023 by Yatharth Gupta

[artvvb]

Hi @Yatharth Gupta

As Jcolvin mentioned, mig.prj files are only to be used with a memory interface generator IP, which is intended to be used with FPGA IO pins connected to DDR memory. The Arty Z7 doesn't have DDR memory that is connected in this way, so a MIG and mig.prj file cannot be used.

You may be able to access Zynq-connected DDR via the Zynq PS's high-performance (HP) AXI slave ports - this would involve AXI buses in the RISC-V design normally connected to the MIG to these ports. That said, this is not a use case we support or have actively tested, so you may run into various unforeseen issues. I would anticipate needing to run some software in the PS to make sure that it is configured correctly, including running the DDR interface and its associated clocks. You will also need to ensure that there are not memory conflicts between the program running in PS and the RISC-V processor. Normal access to other peripherals, like a UART serial connection may also need to be forwarded through the Zynq PS.

Lab two in this coursework put together by a third party (https://digilent.com/reference/programmable-logic/arty-z7/intro-to-fpga) goes over how to instantiate a MicroBlaze soft-core processor in Zynq fabric, and some of the concerns involved, though it does not touch accessing DDR. Still, it may be helpful.

Best of luck,

Arthur