DMA sample duplicates

[Stefanski881]

Hi, i am using the EclypseZ7 with the Zmod scope 1410-105.

My project is based on this example, just in a more basic form  https://digilent.com/reference/programmable-logic/eclypse-z7/demos/ddr-streaming. Basically I just want to stream samples continuously into the memory.

So far it works fine, but when I am reading the samples from the memory, I saw that I get sample duplicates very regularly. Using ILAs I found that the duplication takes place after the AXI SmartConnect IP.

I am using the AXI Direct Memory Access IP in Scather/Gather Mode und I have connected it through the AXI SmartConnect to the ZYNQ7 Processing System. The scope is using 100 MSps and is directly  connected to a AXI-Stream Clock Converter, which converts the clock from 100 MHz to 133 MHz (DDR PLL). In between is a packetizer, which just counts the samples and generates a tlast signal. Using faster/slower clocks doesnt solve the problem, but it changes he pattern. For example with 133 MHz every 2nd sample is duplicated. With 118 MHz every 4th or 5th sample is duplicated. When I am lowering the samplerate it works fine and I get the correct signal, but I need the device to run on 100MSps.

I hope I could explain my problem good enough. If not I can elaborate on it or provide more information.

Thanks in advance.

 

Edited October 4, 2023 by Stefanski881

[artvvb]

Hi @Stefanski881,

Interesting. Does the design meet timing? An intermittent failure like this might mean that data doesn't have enough time to make it to the next register. Any related critical warnings and warnings would be helpful. There are likely various small optimizations that could help.

Thanks,

Arthur

[Stefanski881]

Hey @artvvb, sorry for the late response, I was sick the past week. I dont have any critical warnings. You can see the normal warnings below, that might be related, I was looking into them myself but I am missing some knowledge to fully understand were the problem might come from or what warning could be an issue. 

Edited October 10, 2023 by Stefanski881

[Stefanski881]

I solved the problem. It wasnt any timing issue what so ever. The traitor was the packetizer all along. Basically my rvalid signal was delayed by one clock cycle which caused all the problems.

Sorry for wasting your time, it was a very simple mistake, but still thank you for responding!

Edited October 11, 2023 by Stefanski881