Zmod Eclypse Z7 XDC

[OmerKv]

Hi

I downloaded the XDC file from the following location:

https://github.com/Digilent/digilent-xdc/blob/master/Eclypse-Z7-Master.xdc

I see contradictions between the file and the schematics of the board.

I downloaded a reference design which includes the PS (pod-adc-ltc2264).

From the XDC file of the design there is a pin B7 for adc_out1_p which do not appear in the above file.

I took the design because I didn't find any other reference design which include a PS configuration (DDR, flash and other ports).

Also, as I understand the ZMOD ADC include one ADC but the outputs from ADC A are not connected and instead the outputs from both ADC's are multiplexed as function of DCO state from ADC B

 

Regards

Omer

[Martingu]

Hi,

What are the contradictions you are refering to ? Is it between Digilent's XDC and board schematics or between Digilent's XDC and the XDC from the design you downloaded ?

Where does the design you downloaded come from ?

I have customized the Digilent's XDC file myself for a project and I used the schematics to do so. Both ADC and DAC zmods are working fine and I encountered no contradiction at all between XDC file and schematics.

If you can tell exactly what signals (with the zmod IP signal name) are giving you trouble, maybe I can help.

Guillaume.

[artvvb]

Hi @OmerKv,

Assuming you are using an Opal Kelly SZG-ADC-LTC2264 pod, Digilent doesn't provide example designs for it for the Eclypse, which means that you'd need to port an example design targeting another board (probably some Opal Kelly board) to Eclypse. I would expect that the B7 pin you are looking at is for a demo targeting another board, where the physical pin connections between various peripherals and the FPGA could be different. B7 is likely connected to some pin of the other host board's Syzygy connector. You need to compare the pin locations for the Eclypse and for the other host board, and modify the example design constraints so that the design's ports connect to the physical pin locations for the Eclypse.

There could be other issues that come up as you port the design as well, for example, if the example design includes a Zynq PS configuration, you'd need to make sure to use relevant settings from the Eclypse Zynq preset as well as any relevant settings from the example configuration. Clocking architecture and various other things might also differ, depending on the feature sets of the two boards.

Thanks,

Arthur

[OmerKv]

Hi Arthur

Thank you very much for your prompt reply.

Can you refer me to a reference design by Digilent which include a PS+PL design?

Regards

Omer

[artvvb]

Hi Omer,

Please refer to https://digilent.com/reference/programmable-logic/eclypse-z7/demos/zmod-scope or https://digilent.com/reference/programmable-logic/eclypse-z7/demos/oob.

Thanks,

Arthur

[OmerKv]

On 9/19/2023 at 2:41 PM, Martingu said:

Hi,

What are the contradictions you are refering to ? Is it between Digilent's XDC and board schematics or between Digilent's XDC and the XDC from the design you downloaded ?

Where does the design you downloaded come from ?

I have customized the Digilent's XDC file myself for a project and I used the schematics to do so. Both ADC and DAC zmods are working fine and I encountered no contradiction at all between XDC file and schematics.

If you can tell exactly what signals (with the zmod IP signal name) are giving you trouble, maybe I can help.

Guillaume.

Hi

I am referring to the ADC.

The location of the file: 

https://github.com/SYZYGYfpga/brain-sample-hdl/tree/master/pod-adc-ltc2264

The above design includes a PS which include  the DDR and configuration of the board.

I thought there is a reference design which include PS+PL which will be the base to modify and create design.

As it seems - I may need to modify the XDC, I hope there is no other issues with the PS configuration....

Regards

Omer

[Martingu]

9 hours ago, OmerKv said:

As it seems - I may need to modify the XDC, I hope there is no other issues with the PS configuration....

You just have to change the constraints regarding the PACKAGE_PIN and IOSTANDARD. Digilent AWG and Digitizer Zmods controller IPs include timing constraints (I don't know if it is the same for ADC and DAC Zmods controller IPs but I guess it is).

I attach a constraints file I wrote myself for AWG Zmod on Eclypse's Zmod port A and Digitizer Zmod on Eclypse's Zmod port B.

To build your own constraint file for Eclypse Z7 and Zmods modules, compare the master xdc file (https://github.com/Digilent/digilent-xdc/blob/master/Eclypse-Z7-Master.xdc) with the Zmod schematics. It takes some time but you can see what signal you have to connect to each Syzygy pin (in the xdc file, s[x] is the equivalent to SX on the schematics and d_n[x] is DXN (same for P), see the image bellow). Tip : look at the schematics, master xdc and IP user guide and do not rush things, try to understand before booting the board, you do not want to load bad I/Os constraints.

I have not included the PS in my design yet, all the data to/from DAC/ADC are generated/consumed in the PL. You want the data you send to the DAC to come from the DDR and flow through the PS ?

 

Best regards,

Guillaume.

Eclypse_board.xdc

[OmerKv]

Hi Guillaume

I highly appreciate your prompt reply.

My main concern is regarding the PS pinout.

Xilinx do not include in the XDC the pinout of the PS.

In my project I need to use the DDR (for the configuration - no many pins to look for).

In your project did you use the PS and the DDR?

 

Regards

Omer

[Martingu]

If you instantiate the Processing System IP, you will be able to configure the DDR from there. I do not think you'd have to configure the DDR pinout yourself in your XDC file. I think the processing system IP will manage all those constraints for you.

I am not 100% sure about what I just said, I do not use the DDR in my design, it is PL only for now.

I once worked with Zynq-7000 processing system in the past and I never had to write any constraints linked to the PS pinout (but I have never used the DDR with Zynq-7000).

You want to store the data read from ADC to the DDR memory, is that what you want to do with the DDR ?

[artvvb]

Quote

If you instantiate the Processing System IP, you will be able to configure the DDR from there. I do not think you'd have to configure the DDR pinout yourself in your XDC file. I think the processing system IP will manage all those constraints for you.\

The Zynq preset included in the board files includes all necessary DDR configuration settings, clock settings for the PS, and MIOs. It's applied when you run block automation with the board files installed. This preset is also applied in both of the demos linked previously, one of them could be adapted with different PL IP and constraints modified as needed. Some changes to the Zynq config may be necessary depending on the specifics of the project, like enabling the AXI HP slave ports or setting different FCLK frequencies - AXI HP ports would be necessary for PL access to DDR through DMA, for example.