Martingu

If you instantiate the Processing System IP, you will be able to configure the DDR from there. I do not think you'd have to configure the DDR pinout yourself in your XDC file. I think the processing system IP will manage all those constraints for you. I am not 100% sure about what I just said, I do not use the DDR in my design, it is PL only for now. I once worked with Zynq-7000 processing system in the past and I never had to write any constraints linked to the PS pinout (but I have never used the DDR with Zynq-7000). You want to store the data read from ADC to the DDR memory, is that what you want to do with the DDR ?

You just have to change the constraints regarding the PACKAGE_PIN and IOSTANDARD. Digilent AWG and Digitizer Zmods controller IPs include timing constraints (I don't know if it is the same for ADC and DAC Zmods controller IPs but I guess it is). I attach a constraints file I wrote myself for AWG Zmod on Eclypse's Zmod port A and Digitizer Zmod on Eclypse's Zmod port B. To build your own constraint file for Eclypse Z7 and Zmods modules, compare the master xdc file (https://github.com/Digilent/digilent-xdc/blob/master/Eclypse-Z7-Master.xdc) with the Zmod schematics. It takes some time but you can see what signal you have to connect to each Syzygy pin (in the xdc file, s[x] is the equivalent to SX on the schematics and d_n[x] is DXN (same for P), see the image bellow). Tip : look at the schematics, master xdc and IP user guide and do not rush things, try to understand before booting the board, you do not want to load bad I/Os constraints. I have not included the PS in my design yet, all the data to/from DAC/ADC are generated/consumed in the PL. You want the data you send to the DAC to come from the DDR and flow through the PS ? Best regards, Guillaume. Eclypse_board.xdc

Hi, What are the contradictions you are refering to ? Is it between Digilent's XDC and board schematics or between Digilent's XDC and the XDC from the design you downloaded ? Where does the design you downloaded come from ? I have customized the Digilent's XDC file myself for a project and I used the schematics to do so. Both ADC and DAC zmods are working fine and I encountered no contradiction at all between XDC file and schematics. If you can tell exactly what signals (with the zmod IP signal name) are giving you trouble, maybe I can help. Guillaume.