Gensys2 diff clock route to pmod

[Mustafa]

I have a project that uses external pll to generate clock. I'm routing this clock through diff buffer. I want to make the clock an output from PMOD connector.

I've used JB( in gensys2 manual JA& JB if you want to have differential signals). IOSTANDARD is LVDS_25.

I've used ILA ( integrated logic analyzer) and was successfully see my clock signal. BUT I see nothing when connecting Oscilloscope to pmod.

[zygot]

22 minutes ago, Mustafa said:

I've used JB( in gensys2 manual JA& JB if you want to have differential signals). IOSTANDARD is LVDS_25

What does the schematic tell you about Vccio that powered the IO bank for the pins connected to JA and JB?

What does the Series 7 Select IO User Guide tell you about the available IOSTANDARD types that can be used for signals connected to an IO bank powered by Vccio for the Genesys2 PMOD connectors?

@artvvb,

It's easy to fix documentation mistakes, so why won't anyone change Digilent's habit of telling users of their boards that PMODs can be used for differential signalling when they can't? I've only been trying to get Digilent to stop this for about 10 years by now... and this is obviously a common problem of confusion.

Edited July 24, 2023 by zygot

[Mustafa]

1 hour ago, zygot said:

What does the schematic tell you about Vccio that powered the IO bank for the pins connected to JA and JB?

What does the Series 7 Select IO User Guide tell you about the available IOSTANDARD types that can be used for signals connected to an IO bank powered by Vccio for the Genesys2 PMOD connectors?

It's Kintex-7. PMOD JA & JB are connected to bank 14

I depended only on Diligent documentation

[Mustafa]

2 hours ago, zygot said:

What does the schematic tell you about Vccio that powered the IO bank for the pins connected to JA and JB?

What does the Series 7 Select IO User Guide tell you about the available IOSTANDARD types that can be used for signals connected to an IO bank powered by Vccio for the Genesys2 PMOD connectors?

@artvvb,

It's easy to fix documentation mistakes, so why won't anyone change Digilent's habit of telling users of their boards that PMODs can be used for differential signalling when they can't? I've only been trying to get Digilent to stop this for about 10 years by now... and this is obviously a common problem of confusion.

@artvvb ooh , So Gensys2 cannot provide DS on PMOD.. Please what are the methods to drive DS outside Gensys2?

[asmi]

2 hours ago, zygot said:

What does the Series 7 Select IO User Guide tell you about the available IOSTANDARD types that can be used for signals connected to an IO bank powered by Vccio for the Genesys2 PMOD connectors?

Documentation says that you can receive an LVDS signal on any differential pair regardless of Vccio (that's due to the way LVDS receiver is implemented in silicon). However that's not the full story, there are a bunch of conditions - quoting from UG471:

Quote

Differential inputs for these standards can be placed in banks with VCCO levels that are different from the required level for outputs. There are some important criteria that need to be considered:
a. The optional internal differential termination is not used (DIFF_TERM = FALSE, which is the default value) unless the VCCO voltage is at the level required for outputs.
b. The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet.
c. The differential signals at the input pins meet the VIDIFF and VICM requirements in the corresponding LVDS or LVDS_25 DC Specifications tables in the specific device family data sheet. In some cases, to accomplish this it might be necessary to provide an external circuit to both AC-couple and DC-bias the pins.

The most important of those is (a), as it requires you to have an external termination resistor, which ideally needs to be placed as close as possible to receiver. Not sure what kind of speed can one realistically reach in that kind of environment, but I suspect that you aren't likely to get anywhere near full 1.25 Gbps per pair.

BUT!

JXADC PMOD connector is connected to bank 15, which is powered by VADJ adjustable power supply, so you can technically implement any IO standard that is available in IO cells if you set up your VADJ accordingly. However none of IO pairs connected to JXADC is actually clock-capable, so you can't use JXADC to receive source-syncronous signals, but you can still output them. My guess is that JXADC was designed primarity for LVDS output (as well as analog connections of course).

[asmi]

42 minutes ago, Mustafa said:

ooh , So Gensys2 cannot provide DS on PMOD.. Please what are the methods to drive DS outside Gensys2?

Yes it can, but with some caveats. See my post above for one such way, another way is to use TMDS OUT (which is available at Vccio of 3.3V) and then convert it into regular LVDS using a level converter IC (for example, TI's TMDS1204 or TDP1204).

[zygot]

2 hours ago, Mustafa said:

Gensys2 cannot provide DS on PMOD.

No it can't. But as @asmihas pointed out you can add components to bridge say 1.8V or 2.5V differential signalling using a combination of passive components. You can also just connect LVDS<--> Single-ended components to FPGA single-ended IO.

What you have a problem with is that bitgen will give you an error about incompatible IOSTANDARD assignments to the same bank if you use any of the other IO associated with the same bank as the PMOD signals. These are connected to external components on the board so, you can't pretend that some IO on a bank are 3.3V and others are 2.5V or 1.8V; you can't easily change all of the interface connections to make it all one Vccio Voltage. Lying to the tools about IOSTANDARD (directly) or Vccio ( indirectly ) is a bad idea for a number of reasons. Xilinx has application notes on the subject and I recommend that you read them.

TMDS_33 is of course a valid IOSTANDARD for banks powered with Vccio-3.3V. This may introduce other problems as it requires 50 ohm to ground Vcc terminating resistors ( at the receiving end). This presents a path for one external power supply driving current into a device powered by a separate power supply. Some of Digilent's HDMI board design exhibit issues because of this. But sure, perhaps this is OK for a few use cases.

There are other reasons for why Digilent documentation and marketing is misleading, and I'd so purposely so; here are a few:

• No Digilent FPGA board with so called "high speed differential" PMODs has pads available for you to add any "necessary to provide an external circuit to both AC-couple and DC-bias the pins."
• Digilent offers no PMOD add-on board specifically designed to be used with their own boards sporting these PMOD headers.
• Digilent has never provided a demo or technical note justifying their characterization of referencing these PMOD headers that anyone using any of the boards can implement and test for themselves.

I only have 20 fingers and toes so I've lost count of the number of posts asking the same question as you over the years ( hint: more than 20 ).

Perhaps, you can argue that there are work-arounds for bad designs ( a design that doesn't support the functionality that the vendor claims or purports to suggest that you can expect ) but this is not, in my opinion, a justification for misleading customers. Digilent could decide to provide well designed IO connectors on their boards that support proper multi-signal 1.8V or 2.5V differential signalling; they just don't want to. You don't need a standard like SYZYGY or FMC to do this. Digilent could provideless-than optimal but perhaps usable compensation for 3.3V IO; but the don't want to. Digilent could provide PBC trace length reports for the signals on PMODs using n/p pin pairs,; but they don't. They could just provide theory of design information about how to use these PMODs in custom user applications; but the don't. I'm betting that all of the PMOD signals are assigned to pins after the routing of things like DDR and Ethernet PHY signals are layed out then the auto-router places them. to my knowledge none of the boards' documentation mention whether or not differential pairs are laid out deferentially.

Taking everything into consideration it's hard to see this as anything but misleading to make sales. So, what are they going to do about that perception?

Edited July 24, 2023 by zygot

[asmi]

20 minutes ago, zygot said:

This may introduce other problems as it requires 50 ohm to ground terminating resistors ( at the receiving end).

Not to ground, but to Vccio (+3.3 V)!

[zygot]

2 minutes ago, asmi said:

Not to ground, but to Vccio (+3.3 V)!

Yes, thanks for the correction.

[Ionut]

Hi @Mustafa,

 

As pointed out in the table you posted above, the Genesys 2 board supports on its JA and JB connectors only LVDS_25 input, not output. This means that you can receive LVDS_25 signals in the FPGA using JA and JB, but not send LVDS_25 from the FPGA JA/JB to another circuit. This restriction comes from the fact that the FPGA I/O bank connected to JA and JB is supplied from 3.3V, while LVDS_25 output requires 2.5V (Xilinx UG471, 7 Series FPGAs SelectIO Resources User Guide, Table 1-55).

Since you want to output an LVDS_25 signal from the FPGA, one solution would be to use the JXADC Pmod connector instead, and set the VADJ voltage value to 2.5V using the JP6 jumper. This is necessary since VADJ supplies the FPGA bank connected to JXADC Pmod.

I hope this information is helpful.

Best Regards!

[zygot]

50 minutes ago, Ionut said:

one solution would be to use the JXADC Pmod connector instead

Note that XADC PMODs generally have anti-aliasing filters on the differential signals as these are generally used for the 1 MHz ADC sampler. In the case of the Genesys2, the capacitor is listed as "no load". The pads aren't visible on the bottom of the board ( or I should say that I couldn't find them ). If there are on the top of the board, then the heat sink hides them. There are still 100 ohm series resistors between the JXADC header and the FPGA pins for all of the signals that need to be taken into account if you use them as general IO. Curiously, Digilent doesn't refer to the JXADC header as a "high speed differential" PMOD. I guess that giving up the use of the XADC to acquire external analog signals might be a good trade-off for a board with supposedly "high-speed differential" PMODs that can't be used for differential signalling.

[zygot]

1 hour ago, Ionut said:

This means that you can receive LVDS_25 signals in the FPGA using JA and JB

How was this tested and characterized by Digilent? Can you supply the test setup and documentation?