A couple of questions regarding Arty A7

[asmi]

Here is a section of Arty A7 photo:

What are these things for? The ones on the bottom look like differential pairs, but since all other vias are covered with solder mask, these were obviously left open for a reason. Now I'm curious what these are for :)

Another unrelated question - the "Features" page of Arty A7 board advertizes presence of GTP transcievers:

The problem is that it's factually incorrect, because the CSG324 package doesn't bond out any MGTs as per Xilinx/AMD datasheet:

 

[artvvb]

5 hours ago, asmi said:

Another unrelated question - the "Features" page of Arty A7 board advertizes presence of GTP transcievers:

This has been cut from the page, thanks for the report. We've also removed the same incorrect feature callout from the USB104 A7 page. The I/O slices entry has also been cut from both, as it was a meaningless spec when looking at an FPGA board with all of the I/O pins routed (or not) to specific peripherals. They were likely due to a misreading of the 7-series product selection guide (https://docs.xilinx.com/v/u/en-US/7-series-product-selection-guide).

As for the first question, I'm not sure and have passed it on to a coworker who might know more.

Cheers,

Arthur

[asmi]

31 minutes ago, BMiller said:

The following conversation might help answer your second question. In short, while the chip has the GTPs, they are not bonded to any pins in that package.

I know that, my question was why their presence is advertised as a feature, while they infact are not available?

31 minutes ago, BMiller said:

However, a SelectIO pin is probably good enough for most purposes.

That statement is not even close to being true. Some people choose boards specifically for MGTs exactly because they need them, so it can be a nasty surprise if they read the "features" section and conclude that they are available (otherwise what's the point to advertise them?), and will end up getting a bad surprise to find out that they are infact not available.

Edited July 19, 2023 by asmi

[BMiller]

The following conversation might help answer your second question. In short, while the chip has the GTPs, they are not bonded to any pins in that package. However, a SelectIO pin is probably good enough for most purposes.

https://support.xilinx.com/s/question/0D52E00007FSfYpSAL/xc7a100tcsg324a-gtp-pinout?language=en_US

[zygot]

19 minutes ago, BMiller said:

a SelectIO pin is probably good enough for most purposes.

As for Select IO pin being "probably good enough for most purposes" I'm flummoxed by that statement... it's just so wrong in so many ways. If connecting PMOD headers to PMOD boards is "good enough" then, yeah perhaps this is correct.

As for the confusion with the 6.6 GB/s GTP transceivers. The maximum rate for Artix GTP transceivers is 6.6 Gb/s, but this is only for speed grades that don't appear on any Digilent Artix FPGA board. One might be tempted to assume that that this is an innocent mistake... reading the wrong Xilinx brochure.  The problem is that suggesting a capability that isn't a possibility for their products happens way more often than one would think that simple mistakes are involved.

The problem is that Digilent sell cheap boards to a mostly student or hobbyist clientele. Asmi, knows the answer to his questions because he knows to read the schematics and is familiar with how many Xilinx documents it takes to really know what you can to do with any particular FPGA device in a particular package. What kind of company tries to take money from kids in exchange for promises that can't be kept? Are students supposed to find all of the relevant documentation to figure this out for themselves? Professional engineers? Yeah, if you buy something that can't do what the advertising says ti can do, then shame on you. But students who can't afford textbooks? Really?

With respect to vias that have no purpose; surely even Digilent does automated PCB connectivity and short testing. ??

[zygot]

Along the lines of over-promising marketing, you only need to read one document to be confused. If all you look at is the 7 Series product selection guide, Xilinx tells you that every Artix device has a PCIe Gen2 block and 6.6 Gb/s GTP transceivers. Of course, if you keep downloading more documents you find that not all packages have MGT banks or transceiver pins, or that PCIe Gen2 with a maximum data rate of 3.75 Gb/s or without any transceivers isn't possible.

That's no excuse Digilent.

[zygot]

26 minutes ago, asmi said:

Some people choose boards specifically for MGTs exactly because they need them, so it can be a nasty surprise if they read the "features" section and conclude that they are available (otherwise what's the point to advertise them?), and will end up getting a bad surprise to find out that they are infact not available.

Digilent has been doing this since the Genesys Virtex 5 days. Who'd make a Virtex FPGA board and not allow users access to the transceivers? Oh,Oh... I know...

Never never buy technology without doing your homework. Sometimes, this is a LOT of reading...

 

Edited July 19, 2023 by zygot

[BMiller]

3 hours ago, asmi said:

I know that, my question was why their presence is advertised as a feature, while they infact are not available?

Good point, I misread your question. Really, if one doesn't have access to the GTP pins, is there any advantage to Artix over Spartan? I mean the Digilent boards are different, but at the chip level I only see minor differences between the two other than GTP support. What am I missing?

 

[zygot]

2 hours ago, BMiller said:

I only see minor differences between the two other than GTP support. What am I missing?

Quite a bit. Spartan 6 has a hard multi-channel external memory controller, Series 7 makes you implement it all in logic resources. For small devices this can be significant. In a few metrics Spartan 6 is superior to Artix. Artix has more memory and a better clocking resources. That's only a few differences. It all depends on what you want to do. Same advice for choosing an FPGA board applies to selecting an FGPA device; do you homework. I doubt that designing a new product with Spartan 6 would be a very good move.

Edited July 20, 2023 by zygot

[zygot]

2 hours ago, artvvb said:

This has been cut from the page, thanks for the report.

Why does a customer have to call this to your attention in order to get misinformation corrected, in a piecemeal fashion? Someone at Digilent should be doing this, hopefully before it appears on your websites. Isn't anyone who works for Digilent embarrassed enough to want to do this instead of waiting for a forum post?

Edited July 20, 2023 by zygot

[asmi]

3 hours ago, BMiller said:

Good point, I misread your question. Really, if one doesn't have access to the GTP pins, is there any advantage to Artix over Spartan? I mean the Digilent boards are different, but at the chip level I only see minor differences between the two other than GTP support. What am I missing?

Some Artix devices have higher DSP/logic and BRAM/logic ratio, which might be important for some designs, but otherwise (ignoring GTPs) they complement each other as far as packages/densities go, but of course that fact is not relevant for those who only buy premade boards. Basically Spartan-7 tend to have more IOs available for the same density, while Artix focuses more on computing resources. For example, S75/S100 devices in 484 and 676 ball packages have enough IO to create a moster dual-channel SODIMM DDR3 controller for massive 128 bit of a total data bus running at 400 MHz, while on Artix side this is only possible with the largest A200T device. Artix devices also exist in speed grade 3, which are a bit faster than SG2 and have some unique capabilities (like driving DDR3 at 533 MHz instead of "usual" 400 MHz which is what most Artix-7 and all Spartan-7 devices are capable of).

[asmi]

3 hours ago, artvvb said:

This has been cut from the page, thanks for the report. We've also removed the same incorrect feature callout from the USB104 A7 page.

Thank you, especially for being proactive. I don't search for these on purpose, but I'm often asked about your products, so I have to refer to your store descriptions since I can't remember each and every detail about all of them.

3 hours ago, artvvb said:

The I/O slices entry has also been cut from both, as it was a meaningless spec when looking at an FPGA board with all of the I/O pins routed (or not) to specific peripherals.

Yeah, I've been pondering the relevance of this information to pre-designed boards as well, and it didn't make much sense to me, but I frankly forgot to mention that after I was asked for umteenth time about getting access to GTPs on Arty A7 boards, so that I went onto its' store page searching for cues as to where these questions might be coming from.

[zygot]

10 hours ago, asmi said:

forgot to mention that after I was asked for umteenth time about getting access to GTPs on Arty A7 boards, so that I went onto its' store page searching for cues as to where these questions might be coming from.

I don't know what you will be telling people who ask about transceivers, but here's some context.

Before Series 7 devices, a T in the family device part number meant that it had a transceiver. So you could buy a board with the XC6SLX45T and knew that the device had GTP transceiver(s), even if the board didn't. You could also buy a board with a XC6SLX45 device and know that it had no transceivers.  For reasons unknown, when Xilinx released the Series 7 product line, it decided that it would be less confusing if all family part numbers would include a T in the product number, whether transceivers were available or not. I suspect that it's cheaper to make all of the devices with transceivers even if you have parts in packages that don't provide them to pins or balls.

AMD/Xilinx currently has a different cost optimized product selector guide that shows this ( separate from its Series 7 version ) that includes the Spartan6 through Ultrascale families. At least AMD is careful to include the fine print that says, and I quote: "Important: Verify all data in this document with the device data sheets.". This is splattered all over most pages providing an overview of the part capabilities. By the way there are no Spartan 7 "T" devices and no transceivers on any Spartan 7 device.

So, that's where the confusion comes from.

Then there are product vendors using these devices who really couldn't be bothered with figuring out if what they are telling potential customers in their advertising is true or not, even though whoever designed the products certainly knows.

Is this what you will be telling people who keep asking why they can't get access to GTPs?

So, Digilent has gotten customers posting this very question, to Digilent's forums, about how to use the transceivers in their CMOD A35T ( since at least a year ago ) and no one has thought that perhaps they should change their marketing to clarify that no, you can't use the transceivers on the CMOD A35T or most of their other Series 7 boards.

@asmi you should feel special, because at least someone at Digilent is "proactive" when you point this out.

@artvvb, if you really care about whether or not your company is misleading its customers with its promotional documentation and demo links, all you have to do is spend more time pretending to be a customer and reading what's in the links to Digilent products. Evidently, fixing errors isn't a big deal.

Edited July 20, 2023 by zygot

[asmi]

1 hour ago, zygot said:

AMD/Xilinx currently has a different cost optimized product selector guide

I chuckle every time I see/hear them mention that. In what other industry one can call $800 chips "cost optimized" with the straight face and won't end up promptly laughed away?

[BMiller]

56 minutes ago, asmi said:

I chuckle every time I see/hear them mention that. In what other industry one can call $800 chips "cost optimized" with the straight face and won't end up promptly laughed away?

It's optimized for the manufacturer, not the customer.

[zygot]

1 hour ago, asmi said:

In what other industry one can call $800 chips "cost optimized" with the straight face

You mean like the PC CPU/GPU industry?

It's all relative. Virtex, which can easily be in the $50K+/unit price range, isn't cost optimized. It's also not for customers who care about cost. Digilent isn't going to be selling a Virtex 7 or Virtex UltraSale+ board anytime soon. Digilent isn't going to selling a board with anything from the higher end of the "cost optimized" portfolio. Digilent isn't even going to be selling a Artix UltraScale+ board. Digilent does sell the Genesys2 with a -2 Kintex 325T. In low quantities these are more than $800 a pop. No doubt that Digilent gets preferred pricing for those devices. KIntex isn't cost optimized. Is a -1 Kintex 160T better than a -1 Artix 200T? I suppose the answer depends on what you want to do with it. GTH transceivers are certainly better than GTP transceivers, if your board lets you take advantage of them.

What I don't find particularly humorous is that the free version of VIvado support the following Kintex, Kintex UltraScale and Kintex UltraScale+ devices: XC7K70T,XC7K160T,XCKU025,XCKU035,XCKU3P and XCKU5P. Quick, name all of the reasonably priced FPGA boards with one of these that you can buy today. I know of a couple of XC160T, and these aren't cheap.

How about Artix? Quick, name all of the boards with a XCAU10P,XCAU15P,XCAU20P or XCAU25P, other than Opal Kelly ( assuming that you happen to be lucky enough that they have any ready to ship to you with a delivery date upon order ) that you can buy.

It's always been the case that "cost optimized" means whatever FPGA vendors want the phrase to mean. I the past FPGA vendors have always wanted to be in the commodity or low cost programmable space. I believe that those days are, for the most part gone.

 

 

Edited July 20, 2023 by zygot

[asmi]

4 hours ago, zygot said:

, if you really care about whether or not your company is misleading its customers with its promotional documentation and demo links, all you have to do is spend more time pretending to be a customer and reading what's in the links to Digilent products. Evidently, fixing errors isn't a big deal.

I see no reason to suspect malice when simple incompetence would do. Do you really expect everyone in sales and marketing department to be experts on FPGAs?

[zygot]

53 minutes ago, asmi said:

I see no reason to suspect malice when simple incompetence would do. Do you really expect everyone in sales and marketing department to be experts on FPGAs?

When incompetence is rare, random and quickly addressed then I certainly see it as an honest mistake. When it's endemic and there's a general refusal to address mistakes, especially when they tend to be in favor of the selling party, then I tend to need some convincing evidence that that it doesn't exist for monetary gain. The appearance of Incompetence is sometimes a used as a cover for bad behavior. The Digilent engineers who post to the forums are certainly capable of separating fact from fiction. I'd be surprised if they create marketing content.

So, do I expect that what gets seen by consumer eyes to be factual and not misleading? Yes, especially when the primary market is consumers who are not able to know how to figure all of this out for themselves. 

You have pointed out 2 issues in the last couple of months and Art has resolved them quickly. That's great! I've been pointing out similar misrepresentations over the past 8 years or so and largely they've been ignored. It's not about me, who has no excuse for being mislead by confusing or blatantly incorrect information expressed as official Digilent marketing or documentation. It's about people who don't have the knowledge to protect themselves. Do I expect a company like Digilent to care about those customers as much as I do? Well, yes I do.

I'm not talking about things like sloppy, non-professional documentation that sometimes creep into things like user guides and master constraint files here. I'm talking about things that make a company that have the appearance of being a less than trust-worthy company to do business with. I've bought an awful lot of Digilent products over the years. I'd like to continue to do so.

I'm not accusing anyone of fraud or malice. I'm just pointing out that there's a simple way to convince everyone that those intentions aren't at work.  Frankly, I we shouldn't even be having this discussion. If I were running such an organization it wouldn't be a continuing issue that reflects badly on its engineers who, I believe, are really just trying to do their job as best the can, given the environment in which to do it.

Edited July 20, 2023 by zygot

[artvvb]

On 7/19/2023 at 10:27 AM, asmi said:

What are these things for? The ones on the bottom look like differential pairs, but since all other vias are covered with solder mask, these were obviously left open for a reason. Now I'm curious what these are for :)

I asked one of the design engineers involved. He doesn't recall any particular reason for those vias to be unmasked and indicated it was potentially just an oversight from the engineer who did the layout. They're connected to Pmod port JC or JD.

[asmi]

28 minutes ago, artvvb said:

I asked one of the design engineers involved. He doesn't recall any particular reason for those vias to be unmasked and indicated it was potentially just an oversight from the engineer who did the layout. They're connected to Pmod port JC or JD.

Interesting, moreso that this board went through so many revisions (I have the original Arty, back from the days when it was called simply "Arty", not "Arty A7"), and yet this wasn't changed. But I guess don't fix what ain't broken 😉