This design requires more RAMB36/FIFO cells than are available in the target device.

[smarano]

hi, 

i'm trying to create a simple desing with a microblaze and a custom IpCore with axi stream comunication, but when i try to implement it, Vivado show me the followingmessage :

"[Place 30-640] Place Check : This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 53 of such cell types but only 50 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device."

how i can fix it? 

[D@n]

Easy: use less inferred RAM.  Your internal RAM size is too large.  For example, in Verilog, you might have a ...

reg [31:0] mem [0:4095];

to declare a memory within your application.  Drop the 4095 down by a factor of two and you'll be golden.  You might need to look at how much RAM you've given to microBlaze, perhaps it's more than you need?  Either way, your design is using more block RAM than you have.

Dan