Data transfer from PL to PS DDR

[Waqas Ur Rehman]

We are using Zynq in our vivado project. We want to move some data from PL side to PS DDR through the control of PL side. We are using AXI datamover IP to transfer data from PL to PS DDR. However, we are not able to see any data in PS DDR after PL has provided data on Streaming Interface of AXI datamover IP. We are using Vitis software to see PS DDR contents.

 Can anyone suggest a solution to this problem??

 

[zygot]

Forgetting to disable caching is one common mistake.

[artvvb]

Invalidating the cache for the range that the data has been placed in could also be sufficient. The xil_cache.h driver has the necessary functions. It's a pretty common issue folks run into with DMA as well.

Thanks,

Arthur

[asmi]

34 minutes ago, artvvb said:

Invalidating the cache for the range that the data has been placed in could also be sufficient. The xil_cache.h driver has the necessary functions. It's a pretty common issue folks run into with DMA as well.

There is a potential trap in this though when your buffer is not aligned to a cache line, in that the Xil_DCacheInvalidateRange function not only invalidates the cache lines, but it also flushed them if they were updated by CPU, which could mess with the data that shares the same cache line as other variables which were modified (because cache only tracks modifications on a level of cache lines, and not individual bytes/words of data within those lines). Please refer to this post for more details: https://support.xilinx.com/s/question/0D52E00006iHjkGSAS/zynq-invalidating-a-specific-area-of-data-cache-without-flushing-its-content?language=en_US One way to combat this is to allocate your buffer statically and ensure cache line alignment, but it's not always possible.

Edited July 12, 2023 by asmi