Pmod I/O boards and example IP from Digilent

[captainmark]

Hello,

Will the older IP examples for the Pmod I/O boards( like NAV, USBUART, OLLED, etc. ) work with Xilinx Vivado and Vitis 2019.2? I did see where it said only 2018.1 and older ver but thought I would ask.

Thank You

[artvvb]

Welcome to the forums.

Official support is for 2019.1 and older, pre-Vitis. The sources from the vivado-library master branch are most likely to work, but there hasn't been thorough testing in any version newer than 2019.1.

There are a couple of known issues:

SD and WIFI do not work in Vitis, since it introduced some compiler changes (not sure of exact details) when it first came out that broke all of the software drivers. Most of the drivers were updated some time after that to fix that particular bug, but those two were not fixed. If you do run across this - it can present as generic "makefile errors" but is related to wildcard patterns in how the makefile figures out which headers/sources to use - one way to work around it is to copy all driver sources into an application project's src folder, and potentially modify include paths. This is painful to try for the two mentioned Pmods though, since they involve pretty extensive driver sources.

Board tab automation has problems in some versions, which can show up as either the bottom four pins of a Pmod port failing to have constraints applied (as seen here: https://forum.digilent.com/topic/24263-critical-warning-regarding-board-value/#comment-71596). Workarounds like making the Pmod port external and manually constraining it can work, as seen in the linked thread. 

 

Thanks,

Arthur

[captainmark]

Thank you Arthur

I have tried to get the IP(NAV,OLEDrgb and GPS) working the problem on all three is the connection to the pmod connecter on the board(Zybo Z7). validate design has errors.(see below).

[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /PmodGPS_0/Pmod_out_pin10_i /PmodGPS_0/Pmod_out_pin1_i /PmodGPS_0/Pmod_out_pin2_i /PmodGPS_0/Pmod_out_pin3_i /PmodGPS_0/Pmod_out_pin4_i /PmodGPS_0/Pmod_out_pin7_i /PmodGPS_0/Pmod_out_pin8_i /PmodGPS_0/Pmod_out_pin9_i

[BD 41-49] Could not find abstraction definition for the interface: Pmod_out

It seems that vivado can not find definition for the connector output.

Thanks