captainmark

Thank you Arthur I have tried to get the IP(NAV,OLEDrgb and GPS) working the problem on all three is the connection to the pmod connecter on the board(Zybo Z7). validate design has errors.(see below). [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow. Please check your design and connect them as needed: /PmodGPS_0/Pmod_out_pin10_i /PmodGPS_0/Pmod_out_pin1_i /PmodGPS_0/Pmod_out_pin2_i /PmodGPS_0/Pmod_out_pin3_i /PmodGPS_0/Pmod_out_pin4_i /PmodGPS_0/Pmod_out_pin7_i /PmodGPS_0/Pmod_out_pin8_i /PmodGPS_0/Pmod_out_pin9_i [BD 41-49] Could not find abstraction definition for the interface: Pmod_out It seems that vivado can not find definition for the connector output. Thanks

Hello, Will the older IP examples for the Pmod I/O boards( like NAV, USBUART, OLLED, etc. ) work with Xilinx Vivado and Vitis 2019.2? I did see where it said only 2018.1 and older ver but thought I would ask. Thank You