Critical Warning regarding board value

[Udayan Mallik]

@artvvb I receive the following Critical Warning when I synthesize my design. I am not sure what a pmod_bridge _0 is however I read in one of the posts that you can ignore warnings like this from vivado. Can I ignore a critical warning?

 

[IP_Flow 19-4965] IP pmod_bridge_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:eclypse-z7:part0:1.1'. Please update the project settings to match the packaged IP.

[JColvin]

Hi @Udayan Mallik,

I am not certain which exact error you are getting as I cannot see the error code in the Message console in your screenshots.

If I had to guess as what error your receiving, my guess would be that Vivado is saying that it cannot properly connect the pins 7, 8, 9, and 10 of the Pmod AD1. You can fix this by deleting the "pmod_jb" port and then right-clicking on the Pmod Out interface and choosing the Make External option.

After the interface has been made external and you make the wrapper for the project, you can find the correct names to explicitly name the Pmod pins in the .xdc by finding their names in the wrapper.v file. There are a couple of screenshots showing what I am attempting to describe in this post here:

Please let me know if you have any questions about this process.

Thanks,
JColvin

[JColvin]

Hi @Udayan Mallik,

This critical warning stating that the pmod_bridge was packaged for a different board value can be safely ignored. Basically, the Digilent Pmod IPs during creation were made and tested on a particular board/part (because Vivado forces you to choose a part during project creation), but the pmod_bridge itself is not inherently limited to any particular board.

Let us know if you have any questions.

Thanks,
JColvin

[Udayan Mallik]

@artvvb One of the Critical Warning Messages, generated by the Synthesis engine, and one which @JColvin asked me to ignore - is causing a failure downstream - when I generate a Bitstream for the FPGA. The two attached images show the warning message and the failure message in Vivado.

[Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["/home/udayan/Eclipse_LC402/Eclypse-Z7-LC402/Eclypse-Z7-LC402.gen/sources_1/bd/lc402_Analog/ip/lc402_Analog_PmodAD1_0_0/lc402_Analog_PmodAD1_0_0_board.xdc":4]

The Post titled "Pin assignment Problem - SD Card PMOD." recommends rebuilding the offending module. Can you rebuild the PmodAD1 module for the Eclypse Z7 card?

Edited November 10, 2022 by Udayan Mallik

[Udayan Mallik]

@artvvbI found this post on the Xilinx Forum that goes into why PIN definitions do not percolate up to the Top level. I do not see any difference between the implementation for ACL2 and AD1 Pmods. Continuing to look.

https://support.xilinx.com/s/article/62876?language=en_US

Edited November 16, 2022 by Udayan Mallik

[Udayan Mallik]

@JColvin Declaring the pins as "External Pins" has resolved the issue. Thank you.

Edited December 2, 2022 by Udayan Mallik