ARTY A7-35 - Baremetal Software Projects MIG error on generated xdc file

[Sunny]

Hello,

I am using the Arty A7-35T board and follow through the Baremetal Software Projects tutorial on Vivado 2023.1

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

I have successfully complete the tutorial.

During implementation, the generated file

c:/project/Xilinx/Arty_a7_test1/Arty_a7_test1.gen/sources_1/bd/design_1/ip/design_1_mig_7series_0_0/design_1_mig_7series_0_0/user_design/constraints/design_1_mig_7series_0_0.xdc (Attached)

Line 548: the PACKAGE_PIN E3 should be LVCMOS33.  However, the generated file use LVCMOS25 which caused an implementation error.

(Do not have this issue when using Vivado 2020.1)

How can I change the setting that the generated file for PACKAGE_PIN E3 will be LVCMOS33.

Thanks 

design_1_mig_7series_0_0.xdc

[digiuser1970]

Generally these mismatches regarding voltage settings can be caused by a default voltage setting which is applied for pins which are not explicitely constrained. Not sure if this is the error here.

A question of mine: Where did you derive this XDC from?  It seems to be the MIG's output. How did you setup the MIG to be sure to adapt to the wiring Digilent applied at the PCB?