Zybo Z7 Pmod configuration tutorial

[feplooptest]

Hi

I want to connect Zybo SOC(Petalinux) to a TPM kit below via Pmod.

https://www.avnet.com/opasdata/d120001/medias/docus/187/PB-AES-PMOD-TPM20-SLB9670-G-v5.pdf

However, it is not very clear to me how to configure Pmod so that Zybo SOC SPI can communicate with my TPM kit. From following page, it seems to me that this tutorial is for earlier version. Is that any doc on how to configure Pmod? Does it still require loading a bitstream to connect TPM on Pmod to SPI bus of Zybo SOC?

https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start

Thanks

[artvvb]

Hi @feplooptest

Even in older tool version, IP cores for each Pmod are generally only compatible with the corresponding Pmod. We haven't worked with the TPM20 internally, but I'd recommend running through this guide, which will show how you can connect Xilinx cores to external ports and constrain those ports to any pin on the FPGA (it uses AXI GPIO instead of some SPI controller, but the process is largely the same). You might be able to use a Xilinx AXI QSPI IP core to control this Pmod, however, it will require close attention to the timing requirements of the IP core and the Pmod, as well as the serial interface structure of the main IC on the Pmod's registers.

A PS SPI controller connected to a Pmod port through EMIO might also work, but again depends on the specifics of the TPM SLB 9670.

Thanks,

Arthur

[feplooptest]

Hi @artvvb

I've followed that tutorial to the point that I can look at the option of Pmod configuration in Vivado. However, Pmod JF is not listed and I wonder does that mean Pmod JF is fixed to MIO and can not be modified? 

Thanks for you help

[artvvb]

Correct, the MIO Pmod port is not accessible from PL. You can potentially connect various PS controllers to its pins through the Zynq block's MIO configuration. Refer to this section of the reference manual to see which MIO pins are connected to it: https://digilent.com/reference/programmable-logic/zybo-z7/reference-manual#zynq_apsoc_architecture

Thanks,

Arthur

[feplooptest]

Hi @artvvb

I've gathered SPI signal to MIO pin assignmenet as below:

MISO=PMOD2—>MIO pin 11 

MOSI=PMOD1—>MIO pin 10

CLK=PMOD3—>MIO pin 12

CS=PMOD0—>MIO pin 13

I've found to configure it as below:

But I ran into some critical warning message:

Then a clock error when I tried to validate my block diagram:

I did follow clock configuration as instructed by https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi?_ga=2.123630275.937061154.1687141954-1683228566.1686966320:

Could you please tell me what I did it wrong here?

Thanks for your help

 

Edited June 19, 2023 by feplooptest

[feplooptest]

@artvvb

I found following discussion that resolves my issue above.

https://forum.digilent.com/topic/16877-cora-z7-board-files-m_axi_gp0_aclk-not-connected-to-clock/

Once I generated .xsa file, I imported it into petalinux using below command. Then simply exit gui interface since I don't want additional configuration changes.

"petalinux-config --get-hw-description ~/xilinx/zybo-7010/vivado/PmodIP/TPM_Pmod_wrapper.xsa"

However, I eventually ran into petalinux-build error due to some DTS issues:

Exception: subprocess.CalledProcessError: Command '['dtc', '-@', '-p', '0x1000', '-@', '-i', '/home/leeyuc/xilinx/zybo-7010/os/project-spec/configs/../../components/plnx_workspace/device-tree/device-tree', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work-shared/zynq-generic/kernel-source/scripts/dtc/include-prefixes', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/git/device_tree/data/kernel_dtsi/2022.1/BOARD/', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work-shared/zynq-generic/kernel-source/arch/arm/boot/dts', '-o', 'system-top.dtb', '-I', 'dts', '-O', 'dtb', 'system-top.dts.pp']' returned non-zero exit status 1.                                                                                                                      
 
Subprocess output:                                                                                                                                                                                    
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:52.1-9 Label or path amba_pl not found  
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:92.1-10 Label or path v_tc_out not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:97.1-14 Label or path axi_dynclk_0 not found                                                                                                                                                                                                  
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:103.1-12 Label or path axi_vdma_1 not found                                                                                                                                                                                                   
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:107.1-9 Label or path v_tc_in not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:111.1-12 Label or path axi_vdma_0 not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:115.1-16 Label or path axi_gpio_video not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:119.1-9 Label or path pwm_rgb not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:123.1-9 Label or path amba_pl not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:162.1-15 Label or path axi_i2s_adi_1 not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:184.1-14 Label or path axi_gpio_led not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:189.1-17 Label or path axi_gpio_sw_btn not found
Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:193.1-14 Label or path axi_gpio_eth not found
FATAL ERROR: Syntax error parsing input tree

This looks like the same issue as below:

But the issue persist even if I removed my custom change insisted-usr.dtsi file. Does this mean BSP package is not compatible with my vanilla .xsa created from local Vivado project?

Thanks for your help.

Edited June 20, 2023 by feplooptest

[artvvb]

On 6/18/2023 at 10:35 PM, feplooptest said:

But I ran into some critical warning message:

 

These are ignorable. See the hardware errata section of the reference manual

On 6/18/2023 at 10:35 PM, feplooptest said:

Then a clock error when I tried to validate my block diagram:

 

As seen in the thread you linked, either loop the fclk back to the GP0 clock port, or disable the GP0 interface. GP0 is normally used to control AXI peripherals, so it's enabled in the board files and normally the clock is connected when you use connection automation to connect peripherals, but since GP0 isn't being used here the clock isn't getting connected.

Digilent isn't currently able to provide much help with Petalinux, but you might have some luck with these materials:

https://digilent.com/reference/programmable-logic/zybo-z7/demos/petalinux

https://digilent.com/reference/programmable-logic/documents/git

Based on the linked forum thread, it sounds like the error commonly arises when you use a preconfigured project that is trying to support peripherals not in the hardware design. The petalinux project could be configured to remove those missing peripherals. Presumably, you would also need to make sure that the MIO SPI controller is represented in the petalinux project with a driver attached.

Thanks,

Arthur