feplooptest

@artvvb I found following discussion that resolves my issue above. https://forum.digilent.com/topic/16877-cora-z7-board-files-m_axi_gp0_aclk-not-connected-to-clock/ Once I generated .xsa file, I imported it into petalinux using below command. Then simply exit gui interface since I don't want additional configuration changes. "petalinux-config --get-hw-description ~/xilinx/zybo-7010/vivado/PmodIP/TPM_Pmod_wrapper.xsa" However, I eventually ran into petalinux-build error due to some DTS issues: Exception: subprocess.CalledProcessError: Command '['dtc', '-@', '-p', '0x1000', '-@', '-i', '/home/leeyuc/xilinx/zybo-7010/os/project-spec/configs/../../components/plnx_workspace/device-tree/device-tree', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work-shared/zynq-generic/kernel-source/scripts/dtc/include-prefixes', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/git/device_tree/data/kernel_dtsi/2022.1/BOARD/', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0', '-i', '/home/leeyuc/xilinx/zybo-7010/os/build/tmp/work-shared/zynq-generic/kernel-source/arch/arm/boot/dts', '-o', 'system-top.dtb', '-I', 'dts', '-O', 'dtb', 'system-top.dts.pp']' returned non-zero exit status 1. Subprocess output: Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:52.1-9 Label or path amba_pl not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:92.1-10 Label or path v_tc_out not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:97.1-14 Label or path axi_dynclk_0 not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:103.1-12 Label or path axi_vdma_1 not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:107.1-9 Label or path v_tc_in not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:111.1-12 Label or path axi_vdma_0 not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:115.1-16 Label or path axi_gpio_video not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:119.1-9 Label or path pwm_rgb not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:123.1-9 Label or path amba_pl not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:162.1-15 Label or path axi_i2s_adi_1 not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:184.1-14 Label or path axi_gpio_led not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:189.1-17 Label or path axi_gpio_sw_btn not found Error: /home/leeyuc/xilinx/zybo-7010/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/device-tree/xilinx-v2022.1+gitAUTOINC+1b364a44fa-r0/system-user.dtsi:193.1-14 Label or path axi_gpio_eth not found FATAL ERROR: Syntax error parsing input tree This looks like the same issue as below: But the issue persist even if I removed my custom change insisted-usr.dtsi file. Does this mean BSP package is not compatible with my vanilla .xsa created from local Vivado project? Thanks for your help.

Hi @artvvb I've gathered SPI signal to MIO pin assignmenet as below: MISO=PMOD2—>MIO pin 11 MOSI=PMOD1—>MIO pin 10 CLK=PMOD3—>MIO pin 12 CS=PMOD0—>MIO pin 13 I've found to configure it as below: But I ran into some critical warning message: Then a clock error when I tried to validate my block diagram: I did follow clock configuration as instructed by https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi?_ga=2.123630275.937061154.1687141954-1683228566.1686966320: Could you please tell me what I did it wrong here? Thanks for your help

Hi @artvvb I've followed that tutorial to the point that I can look at the option of Pmod configuration in Vivado. However, Pmod JF is not listed and I wonder does that mean Pmod JF is fixed to MIO and can not be modified? Thanks for you help

Hi I want to connect Zybo SOC(Petalinux) to a TPM kit below via Pmod. https://www.avnet.com/opasdata/d120001/medias/docus/187/PB-AES-PMOD-TPM20-SLB9670-G-v5.pdf However, it is not very clear to me how to configure Pmod so that Zybo SOC SPI can communicate with my TPM kit. From following page, it seems to me that this tutorial is for earlier version. Is that any doc on how to configure Pmod? Does it still require loading a bitstream to connect TPM on Pmod to SPI bus of Zybo SOC? https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start Thanks

Answer my own question. Removing "build" folder of yocto project and re-run petalinux-build fixes above issue.

Hi I am trying to follow the build step in demo page. https://digilent.com/reference/programmable-logic/zybo-z7/demos/petalinux While running petalinux-build command, I am seeing a lot of errors related to python(a small portion shown below). Is there any more packages that I need to install before I can build it? Thanks WARNING: fsbl-1.0-r0 do_deploy_setscene: No sstate archive obtainable, will run full task instead. ERROR: Logfile of failure stored in: /home/leeyuc/xilinx/prj/plinux/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/fsbl/1.0-r0/temp/log.do_deploy_setscene.23492 WARNING: Setscene task (/home/leeyuc/xilinx/prj/plinux/os/components/yocto/layers/meta-xilinx/meta-xilinx-core/recipes-bsp/embeddedsw/fsbl.bb:do_deploy_setscene) failed with exit code '1' - real task will be run instead WARNING: u-boot-xlnx-v2021.01-xilinx-v2022.1+gitAUTOINC+8e8809e33a-r0 do_deploy_setscene: No sstate archive obtainable, will run full task instead. ERROR: Logfile of failure stored in: /home/leeyuc/xilinx/prj/plinux/os/build/tmp/work/zynq_generic-xilinx-linux-gnueabi/u-boot-xlnx/v2021.01-xilinx-v2022.1+gitAUTOINC+8e8809e33a-r0/temp/log.do_deploy_setscene.23509 WARNING: Setscene task (/home/leeyuc/xilinx/prj/plinux/os/components/yocto/layers/meta-xilinx/meta-xilinx-core/recipes-bsp/u-boot/u-boot-xlnx_2022.1.bb:do_deploy_setscene) failed with exit code '1' - real task will be run instead ERROR: udev-extraconf-1.1-r0 do_populate_sysroot_setscene: Error executing a python function in exec_func_python() autogenerated: The stack trace of python calls that resulted in this exception/failure was: File: 'exec_func_python() autogenerated', lineno: 2, function: <module> 0001: *** 0002:do_populate_sysroot_setscene(d) 0003: File: '/home/leeyuc/xilinx/prj/plinux/os/components/yocto/layers/core/meta/classes/staging.bbclass', lineno: 132, function: do_populate_sysroot_setscene 0128:do_populate_sysroot[sstate-outputdirs] = "${COMPONENTS_DIR}/${PACKAGE_ARCH}/${PN}" 0129:do_populate_sysroot[sstate-fixmedir] = "${COMPONENTS_DIR}/${PACKAGE_ARCH}/${PN}" 0130: 0131:python do_populate_sysroot_setscene () { *** 0132: sstate_setscene(d) 0133:} 0134:addtask do_populate_sysroot_setscene 0135: 0136:def staging_copyfile(c, target, dest, postinsts, seendirs): File: '/home/leeyuc/xilinx/prj/plinux/os/components/yocto/layers/core/meta/classes/sstate.bbclass', lineno: 789, function: sstate_setscene 0785: 0786: 0787:def sstate_setscene(d): 0788: shared_state = sstate_state_fromvars(d) *** 0789: accelerate = sstate_installpkg(shared_state, d) 0790: if not accelerate: 0791: msg = "No sstate archive obtainable, will run full task instead." 0792: bb.warn(msg) 0793: raise bb.BBHandledException(msg) File: '/home/leeyuc/xilinx/prj/plinux/os/components/yocto/layers/core/meta/classes/sstate.bbclass', lineno: 358, function: sstate_installpkg 0354: sstatefetch = d.getVar('SSTATE_PKGNAME') 0355: sstatepkg = d.getVar('SSTATE_PKG') 0356: 0357: if not os.path.exists(sstatepkg): *** 0358: pstaging_fetch(sstatefetch, d) 0359:

Thank you very much for the information.

Hi Does anyone know if any of Digilent's board support partial reconfiguration? It looks like following might, but I am not certain about it. ZedBoard Zynq-7000 ARM/FPGA SoC Development Board Thanks for your help