Cora z7, board files, M_AXI_GP0_ACLK not connected to clock

[libor]

Hello.

I have been facing the following issue. I am using Vivado v2018.2.2

1. I installed the board files for Cora z7 board
2. I have created a new project and added a design to it.
3. I added ZYNQ7 processing system to the design.
4. There was a green bar with "Designer Assistance available. Run Block Automation.", that I used.
5. I tried to validate the design.
6. with the following error: "[BD 41-758] The following clock pins are not connected to a valid clock source: /processing_system7_0/M_AXI_GP0_ACLK"

Can you be please of any help?

Thank you very much.

Libor

 

[jpeyron]

Hi @libor,

If you only have the Zynq processor in your block design you will need to connect the FCLK_CLK0 to the M_AXI_GP0_ACLK as  I have done in the attached screen shot.  Please attach a screen shot of your block design if this does not fix the issue.

cheers,

Jon

 

 

 

[libor]

HI @jpeyron.

Thank you so much, Jon. Yes, it worked, I am just surprised that the error message did not disappear (I probably tried that but still seen the error message.).

May I please ask you also about the warning messages? Should I be worried? Or when should I be worried?

[PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 

[PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 

Best,

Libor

 

[jpeyron]

Hi @libor,

Here is Hardware errata section of the reference manual for the zybo-Z7 that explains these errors. I will talk to our content team about adding this section to the other Zynq  Dev Boards reference manuals. You can ignore these warnings.

cheers,

Jon

[libor]

Thank you again @jpeyron .

Cheers,

Libor