can I configure DDR3 on Digilent Artix-7 FPGA Development Board to Dual Channel mode?

[zzzhhh]

There are 256MB DDR3 RAM installed on Digilent Artix-7 FPGA Development Board. Can I configure it to Dual Channel mode?

[asmi]

What do you mean by "dual channel mode"?

[zzzhhh]

Continue to ask.

[zzzhhh]

OK, the answer is No.

[zygot]

It's not clear what you mean by "dual_channel mode"

Let me assume that you are referring to the kind of external memory controller that the Spartan 6 series sported; this hard block could support multiple channels. Using the concept of mode is probably confusing.

The short answer is yes.

Since AMD/Xilinx decided to drop hard DDR controller blocks in its devices they also decide not to provide a soft multi-channel DDR controller either for some reason. The only external memory controller for IP Series7 FPGA devices that Vivado provides is the MIG. This IP actually isn't a complete solution, as the user has to create logic to control the MIG controller. So, yes you can create a multi-channel controller that runs the MIG controller. You need to decide if your channels get access to the external memory using a priority or round-robin scheme. BTW, the Spartan 6 hard controller wasn't a complete solution either; the user has to provide logic to control the controller.

If you want to see a simplistic multi-channel priority driven MIG you can look at the source in this tutorial: https://forum.digilent.com/topic/25315-using-ddr-as-a-video-frame-buffer/ Edited March 31, 2023 by zygot

[zzzhhh]

14 hours ago, zygot said:

It's not clear what you mean by "dual_channel mode"

Let me assume that you are referring to the kind of external memory controller that the Spartan 6 series sported; this hard block could support multiple channels. Using the concept of mode is probably confusing.

The short answer is yes.

Since AMD/Xilinx decided to drop hard DDR controller blocks in its devices they also decide not to provide a soft multi-channel DDR controller either for some reason. The only external memory controller for IP Series7 FPGA devices that Vivado provides is the MIG. This IP actually isn't a complete solution, as the user has to create logic to control the MIG controller. So, yes you can create a multi-channel controller that runs the MIG controller. You need to decide if your channels get access to the external memory using a priority or round-robin scheme. BTW, the Spartan 6 hard controller wasn't a complete solution either; the user has to provide logic to control the controller.

If you want to see a simplistic multi-channel priority driven MIG you can look at the source in this tutorial: https://forum.digilent.com/topic/25315-using-ddr-as-a-video-frame-buffer/

I asked the same question in EE stackoverflow here. I agree on the convincing but discouraging answer so I think the answer is no. After all, the hardware configuration of Arty A7 board is fixed -- there is only a single DDR3 memory chip installed. My purpose is to implement dual-channel architecture and verify that it is really faster than single channel. To that end, an FPGA development board should have multiple DDR memory chips installed. Then we can embed multiple memory controller IP cores that support dual-channel architecture into FPGA (so it is internal). Maybe Digilent has had such a board, but I guess it must be very expensive. Even if I can afford one, putting two MIG memory controllers into FPGA to implement dual-channel may be more challenging than simply embedding one existing mature and complete dual-channel memory controller IP core.

Many thanks for your link. From the filename it seems that it is a dual-channel memory controller IP core aiming at Nexys A7. But Nexys A7 also has only one DDR chip, just like Arty A7. So, how did you realize dual-channel? Did you add any additional circuit to Nexys A7? I'm still new to this area, so maybe I have missed some important point and underestimate the difficulty. Perhaps I will have a deeper understanding in the future after I have studied enough background knowledge. PS, I would like to use round-robin scheme.

[zygot]

OK... so I guessed wrong. Your definition of dual-channel is along the lines of what your PC has, with it's CPU and IO chip-set and all.

FPGA devices have a limited number of IO pins so you aren't going to find many FPGA development boards with multiple banks of external memory, each with their own address, data and control lines. The only exception that I know of is the Cyclone V GT Development board. This one has a 40-bit (DQ) DDR3 bank connected to the Cyclone hard controller and a completely separate 64-bit DDR bank connected to a soft-memory controller implemented in programmable logic. But, and this is a very nice FPGA development board for a lot of reasons, even this board won't suit your purposes. It's kind of like going to the Porsche dealer and asking about their fastest street legal car and, oh by the way I'd like to be able to haul my 20 tons of rock with it, and I need a hydraulic dumper. Two goals requiring separate purpose-designed vehicles...

Your definition of dual-channel is not similar to the one that I used in my previous post. No, it's extremely unlikely that you are ever going to do an FPGA project where you can test the performance of external memory comparing one verses two channels. Now, if you can build you own board that has add-on DDR cards with a transceiver interface to the FPGA device... you might have a chance. 4 lanes of mDP transceivers can definitely transfer more data than 2 lanes of mDP transceivers. But you still have a lot of issues, like coherency to resolve. This really isn't a problem that anyone that I know of wants to solve. Edited April 1, 2023 by zygot

[zzzhhh]

9 hours ago, zygot said:

OK... so I guessed wrong. Your definition of dual-channel is along the lines of what your PC has, with it's CPU and IO chip-set and all.

FPGA devices have a limited number of IO pins so you aren't going to find many FPGA development boards with multiple banks of external memory, each with their own address, data and control lines. The only exception that I know of is the Cyclone V GT Development board. This one has a 40-bit (DQ) DDR3 bank connected to the Cyclone hard controller and a completely separate 64-bit DDR bank connected to a soft-memory controller implemented in programmable logic. But, and this is a very nice FPGA development board for a lot of reasons, even this board won't suit your purposes. It's kind of like going to the Porsche dealer and asking about their fastest street legal car and, oh by the way I'd like to be able to haul my 20 tons of rock with it, and I need a hydraulic dumper. Two goals requiring separate purpose-designed vehicles...

Your definition of dual-channel is not similar to the one that I used in my previous post. No, it's extremely unlikely that you are ever going to do an FPGA project where you can test the performance of external memory comparing one verses two channels. Now, if you can build you own board that has add-on DDR cards with a transceiver interface to the FPGA device... you might have a chance. 4 lanes of mDP transceivers can definitely transfer more data than 2 lanes of mDP transceivers. But you still have a lot of issues, like coherency to resolve. This really isn't a problem that anyone that I know of wants to solve.

So what's your definition of dual-channel mode? Wikepedia says it clearly so I assume that's a commonly accepted concept even in FPGA community. At least I entered a Porsche store and talked about 20 tons hydraulic dumper at very beginning. It is the dealer who knows street legal car only and thought I wanted to buy that.

[zygot]

23 hours ago, zzzhhh said:

So what's your definition of dual-channel mode?

My, evidently poor analogy of a high performance sports car and a dump truck, was meant to convey the difference between a modern PC motherboard and FPGA based hardware, not as a personal slight for asking your question.

The reference link you post above is clearly about motherboard memory capability. Those fancy high end CPUs by AMD and Intel don't do high performance IO directly, but though specialized chipsets. Modern motherboards have slots for 4 or more memory cards with very wide data widths. You aren't going to find such chipsets or DIMM slots on a cheap FPGA board. The concept of multi-channel for a motherboard with 8 DIMMs and 32 GB of memory is foreign to FPGA based hardware that you are going to purchase from a vendor like Digilent. As I pointed out even finding a board with 2 or more banks of DDR3 with separate address and data lines connected to the FPGA is hard to come by.

For low end or mid-range programmable devices can't run DDR3 at optimal data rates so the concept of trying to double the data rate through a specialized controller isn't worth doing.** This might make sense for really expensive CPUs, but not for programmable logic. Each has its own special abilities. This includes programmable logic with embedded processor cores like ZYNQ. Embedded applications, where FPGAs and micro-controllers reign, generally don't include 800 watt power supplies like high end PC hardware.

In the context of FPGA external memory like DDR3, particularly with devices having no hard processor, multi-channel external controllers refer to something implemented in logic and  block memory resources ( MIG soft controller ) or a hard external memory block ( Spartan 6 or Cyclone V ) where the logic application can service more than one data source or sink in the design; though never more than one concurrently. Now the discussion is a bit different for high end PC FPGA based accelerator cards like Alveo  that might have 64 GB of memory; but that's a different kind application arena.

IN theory, you could buy the Cyclone V GT Development board ( the cheapest one that I know of with 2 separate but complete DDR memory banks and issue read or write request to both concurrently and see some aggregate data rate boost. This will still not be functionally equivalent to what the CPU/Chipset combination on a PC motherboard with multi-channel memory controllers can do, though it might well be very useful. Understand that there's a big difference between a multi-core CPU executing instructions and what's (typically) going on in programmable logic.

Words, and especially technical terms, with no context have ambiguous meaning. Hence, for your post, you got one response consisting of just a question, which you ignored, and my response. What would lead you to assume that a Wikipedia article talking about PC motherboards would apply to the FPGA community?

** After having made that statement I remembered that there are a few, fairly expensive, application specific FPGA based boards ( like NetFPGA) for Ethernet connectivity that need concurrent access to separate external memory resources. But these don't do the kind of channelizing that you are thinking of either. Again, context is everything.

 

Edited April 2, 2023 by zygot

[zzzhhh]

OK, I think I have found an answer to what I want. The FPGA is Xilinx Virtex UltraScale+ HBM, and the board is called VCU128. Of course, the price of the board is prohibitive to me, but I can at least simulate it in host PC and acquire some idea of characteristics of multi-channel memory. Each layer of HBM having two channels, think how many channels it has if two 8-layer HBM stacks are installed, and how many if four HBM chips? Enough for my application scenario.

Here I have some words for zygot. First, I thank you for the detailed reply. I don't know if you are an employee of Digilent or Xilinx. If not, I have nothing to say. If you are, as a technical support, your job here is not showing off how much your knowledge is. In stead, your job here is to assist (possibly potential) customers. To that end, in front of a question, you should read, and then try to understand, then think, before answering a question. But you just skim through the question, pick up a few words that you happen to know of, then assume (instead of understand) that this is what the question is asking about, then dumping out what you know about it, totally ignorant of what the asker really wanted to know in his/her original question. Take my original question as an example. What I want is to have an FPGA development environment in which there are multiple memory channels. I did NOT imply that I will simulate a PC and restrict the environment "along the lines of what your PC has, with it's CPU and IO chip-set and all". I know I mentioned DDR3 installed in Arty board, that's because I only knew of DDR as the only type of external memory at the time of asking. But you got excited at this and desperately assumed that I was asking for DDR multi-channel memory, instead of thinking one more step what I really want. So, to repeat, in front of a question, I hope you can read from beginning to end, make sure you understand on the asker's side, think, and finally answer. I don't meant to assail you; I just hope you can do well in your job. Maybe your technical background about DDR is really very strong so many people have to agree with you because they don't even know what you are talking about. But at the same time, you will develop an illusion that once you answer, your answer is correct; other people must agree with you and exactly follow your line of thinking; otherwise, they are simply wrong; you might never thought of a possibility that your answer is correct but not to the point. You are just reciting your knowledge, but not answering. I think this is what you need be be aware of and try to improve. At the end, thanks again for your replies.

[zygot]

11 hours ago, zzzhhh said:

I don't know if you are an employee of Digilent or Xilinx. If not, I have nothing to say.

Not. Perhaps you should have asked before going on with your post. In the Digilent Forums, Digilent employees who post generally identify themselves as such. You can view details about members from the site.

11 hours ago, zzzhhh said:

totally ignorant of what the asker really wanted to know in his/her original question.

I can only reply to questions that are actually asked. This was what you asked: "There are 256MB DDR3 RAM installed on Digilent Artix-7 FPGA Development Board. Can I configure it to Dual Channel mode?". Sometimes, it's reasonable to assume that the question being asked is not getting to the source of the problem that the questioner want to resolve. Sometimes, I "read between the lines" and expand the question. Sometimes, this works out well, and sometimes people get offended and really irritated. Some questions are pretty straight-forward and only one answer is suitable. Often questions require more of a conversation than an answer to get at a good resolution. Answering questions, particularly in this type of venue is fraught with danger.

I get it; you weren't happy with my attempt at having a conversation. Was my reply worse than the other one, which you ignored?

No one can divine what someone else really want to ask with 100% accuracy. The best that can happen in this type of forum is engage in civil conversation and overlook shortcomings in what's being written. Usually a conversation works out in the end. Sometimes, it doesn't.

11 hours ago, zzzhhh said:

OK, I think I have found an answer to what I want. The FPGA is Xilinx Virtex UltraScale+ HBM, and the board is called VCU128.

Maybe, maybe not. I still don't know what it is that you want. I still suspect that you don't know exactly what it is that you want to do. There are a lot of FPGA variations. Digilent certainly doesn't sell the really expensive ones. Programmable devices like the Versal family are suitable for applications that are different than those found on products that Digilent sells. HMB may not be what you assume that it is in the context of this thread. It certainly won't hurt to do some research and figure this out.

I'm sorry that my replies aren't satisfactory to you. When I provide information that I think might be helpful I rely on the fact that anyone reading it might have a better answer. This could still happen to this thread if anyone can figure out what the question that you really want to ask is.

 

Edited April 5, 2023 by zygot