Genesys 2 GTX IBERT

[Naveen]

Hi,

I am having a genesys 2 kintex fpga evaluation board. I am trying to setup the GTX transceivers, on the FMC connector using the IBERT IP core.

From my understanding the external clock is on Pins AD12 and AD11 and is 200MHz LVDS. However, the QPLL fails to lock (when read using chipscopepro). Has someone configured IBERT with this board successfully?

Thanks,

[JColvin]

Hi Naveen,

I personally don't have any experience with IBERT, but I have asked some of applications engineers to see they have worked with that IP core before.

Thanks,
JColvin

[jpeyron]

Hi Naveen,

I'm sorry but we haven't worked with the IBERT IP before. I have been reaching out to see if anyone i know has and i haven't recieved any positive responses. I will let you know if i find someone who has worked with the Ibert IP before. Hopefully someone in the community has and would be able to assist with this. 

thank you,

Jon