Can UART communication be made from any pin of zybo z-7-10

[drkome]

Can UART communication be made from any pin of zybo z-7-10 or any FPGA card? I will be glad if you answer these 2 questions. I burned my card while making uart communication from one pin before. Now I want to ask out of curiosity.

[zygot]

As I mentioned in your other post, I use these kinds of USB UART cables all the time.

You need to connect TxD, RxD, and DGND to use these without hardware flow control. NEVER connect an external power supply to any PMOD Vcc pin. Just make sure that you figure out which direction the TxD and RxD signals are driven. You need a common ground reference between your FPGA board and an external device to guarantee signal voltage levels and as a current return for single-ended signals that are being driven out of the FPGA device and the external device.

I don't know the rules of your competition but it would seem, from what you've mentioned, that an FPGA board that doesn't have a ZYNQ device would be easier to work with. Edited February 28, 2023 by zygot

[zygot]

As I recall, if you damaged your board, it was because you connected an external 5V power source to one the of the PMOD 3.3V rail pins. This has nothing to do with pin functionality.

Most ZYNQ based FPGA boards only use one of the PS UARTs so you can connect the unused one through the EMIO to the PL and then to any IO pin connected to a header on your board. Or you can just connect the unused UART to your PL logic. It's also possible to implement a UART in the the PL logic and allow your PL design to connect to an external device using a direct connection or through a USB UART cable. Any two pins on a PMOD on any FPGA board made by Digilent can be used as a UART interface.

Connecting a PS UART to the PL allows you to use one of the PS cores to implement a UART. The PS UART has some limitations, like very shallow data FIFOs. You can get around FIFO limitations by connecting a PS UART through PL logic. You have even more flexibility by designing your own UART in an HDL, though, if you want to connect this UART to the PS you need to use a AXI bus transport to move data between the PS and PL.

[drkome]

@zygot  Thanks for answer;
I have  pl2303 uart cable,  and this cable have VCC(5V),gnd,TX,RX,  The card is damaged because I connected this cable before. Will it hurt if I connect this cable only to the gnd? Even if I don't connect the 5v volt?. Or is there any other method for zybo z7-10 card for uart? It is easier for uart communication. (Moreover We are participating in the processor design competition. We need to write the wishbone bus and the whole processor as hdl. Including Uart. There will be no use of any ready-made IP or block diagram.)
Thank you so much.

Edited February 28, 2023 by drkome

[engrpetero]

On 2/28/2023 at 9:47 AM, zygot said:

Most ZYNQ based FPGA boards only use one of the PS UARTs so you can connect the unused one through the EMIO to the PL and then to any IO pin connected to a header on your board. Or you can just connect the unused UART to your PL logic. It's also possible to implement a UART in the the PL logic and allow your PL design to connect to an external device using a direct connection or through a USB UART cable. Any two pins on a PMOD on any FPGA board made by Digilent can be used as a UART interface.

Connecting a PS UART to the PL allows you to use one of the PS cores to implement a UART. The PS UART has some limitations, like very shallow data FIFOs. You can get around FIFO limitations by connecting a PS UART through PL logic. You have even more flexibility by designing your own UART in an HDL, though, if you want to connect this UART to the PS you need to use a AXI bus transport to move data between the PS and PL.

This subject is near and dear to my Zybo learning exercise lately so I thought I'd add an additional comment.  The Zynq PS block does have an unused UART (mentioned by @zygot with the mentioned FIFO limitations) that can be connected to MIO pins exposed on the Zybo JF connector (bypassing the PL, if desired).  Of course, to use xil_printf for both UART0 and UART1, some Vitis code changes are needed (seemingly straightforward since the xil_printf functions are easy to duplicate).

[drkome]

@zygot, @engrpetero
So thank you for help.