Using Arty A7 35T board

[Jonathan101]

Hello everyone,

I am using Arty7-35T for a project that once used to work. I have compiled workspace, and I load bitstream from Vitis.

When Vitis program the FPGA and try to load the program an error comes: ERROR : Cannot stop MicroBlaze. Stalled on instruction fetch. PC=0x58 

This is full Vitis log:

Vitis Log:
11:55:58 INFO : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
targets -set -filter {jtag_cable_name =~ "Digilent Arty A7-35T 210319B57F72A" && level==0 && jtag_device_ctx=="jsn-Arty A7-35T-210319B57F72A-0362d093-0"}
fpga -file /workspace/Code_Package/Code_Sample/_ide/bitstream/design_1_wrapper.bit
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
loadhw -hw /workspace/Code_Package/design_1_wrapper/export/design_1_wrapper/hw/design_1_wrapper.xsa -regs
configparams mdm-detect-bscan-mask 2
targets -set -nocase -filter {name =~ "*microblaze*#0" && bscan=="USER2" }
dow /workspace/Code_Package/Code_Sample/Debug/Code_Sample.elf
----------------End of Script----------------

11:55:58 ERROR : Cannot stop MicroBlaze. Stalled on instruction fetch. PC=0x58

 

What can I do to solve this issue? 
 

[JColvin]

Hi @Jonathan101,

Based on this Xilinx Answer Record, https://support.xilinx.com/s/article/66285?language=en_US, this sort of error comes from having a non-default reset vector. How does your addresses ranges you have in Vivado compare to the linker script that you have in Vitis? Main thing from what I have seen in other Xilinx support threads (since I have not encountered this particular issue before) would be to make sure that the offsets used are matching correctly.

Thanks,
JColvin