Zybo Z7 20 external clock for PL

[fenixzhang]

Hi,

I have a Zybo Z7 20. I want to use the external 125Mhz clock from ethernet phy for PL so I can do some simple PL FGPA design without PS coding.

How should I do that?

I assign K17 to the clk pin as input. Assign E17 to clk_en as output and set it to 1.

But I don't get clk signal

[zygot]

When you want to use a ZYNQ based board for just the PL you shouldn't just pretend that the PS isn't there.

The approach that I use for most of my ZYNQ designs is to create a basic ZYNQ system using the IPI GUI. Any signals that I want from or to the ZYNQ subsystem gets exported to an external (PL) connection in the block design. You can do this with the 4 FCLK_CLK outputs sourced by one of the system PLLs. Selecting one of these might be a better choice for your first project. Save the design and have Vivado generate an HDL file representing the ZYNQ system. I don't allow Vivado to manage this file because I want to instantiate it in my own toplevel file. If you export a PS clock into your PL this can become either a global clock or an input to an MMCM or PLL in the PL.

[artvvb]

Hi @fenixzhang

First off, I agree with what zygot has said about how Zynq designs should not ignore the PS. That said, you ought to still be able to use the ethernet clock to clock FPGA logic without touching PL. Driving E17 to logic high shouldn't even be necessary, as the pullup resistor is there to handle that for you, as long as the FPGA isn't actively pulling the line down.

How did you determine that the clock wasn't working?

The following dead simple test design works fine on my hardware, with and without the eth_rst_b port.

Verilog module:

`timescale 1ns / 1ps
`default_nettype none

module top (
    input wire clk,
    input wire btn,
    output reg led,
    output wire eth_rst_b
);
    always@(posedge clk) begin
        led <= btn;
    end
    assign eth_rst_b = 1;
endmodule

XDC file:

set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led }]; #IO_L23P_T3_35 Sch=led[0]
set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=eth_rst_b

Thanks,

Arthur

[Richm]

Dunno, I've experimented with many PL only designs but I always use the PL clock & a clock wizard. If you click on the 'board' tab with the block design open, you should see a clock source listed that you can click on and add to your design. It will create the necessary ports, constraints and a clock wizard that you can modify. Note that by PL only I mean no PS in the block design and using the Vivado hardware manager only.

[fenixzhang]

Hi @artvvb Thanks for the feedback! I download the zybo source file later and it works. Here is the clock setting in xdc file

#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
#create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];

[artvvb]

Your clock might not actually be getting constrained at all - the "#" characters at the start of each line comment out those lines. The name "sysclk" in brackets passed to get_ports also needs to match your top module's clock port's name, like how I renamed it to "clk" in the posted sources above.