XADC in Arty A7 100T

[Manan Oza]

We am new to FPGA and XADC. We have recently got arty a7 100t fpga board.

I am trying to run through example code given by digilent in following web page: https://digilent.com/reference/programmable-logic/arty-a7/start?redirect=1

We have completed Arty A7 General IO Demo, and it is running fine.

We tried to run Arty A7 XADC Demo, but it is not working. After loading bit file to board LEDs are working.

We have tried with XADC temperature which is working fine but when we tries to use external pin for XADC, it is not working.

Please help us to solve the issue.

 

Thanking in advance,

regards,

Manan

[artvvb]

Hi @Manan Oza

I suspect that some unnecessary bad_address logic in the verilog source is causing XADC transactions to not be restarted. If the switch value ever goes above 8, bad_address gets asserted and masks out all future end of conversion signals, which are normally used to trigger the DRP enable port to start a read. It breaks the continuous conversion XADC setup.

Removing this logic, by cutting the bad_address instantiation on line 34, modifying the port connection to den_in to only "enable" on line 45, and cutting lines 112 through 115, should fix the problem.

This has been corrected in this release: https://github.com/Digilent/Arty-A7/releases/tag/100/XADC/2022.1-2

Thanks,

Arthur

[Manan Oza]

Thanks Arthur @artvvb,

I tried with your suggestion as given in para 2 and 3 of your reply, but LED is not working.

Temperature ADC is working fine but A0 (VAUXP4_VAUXN4) not working. Other Analogue Inputs (from external pins) are also not  working.

I tried using XADC (System monitor) with no success. (screen shot attached)

 

Thanks for your time and interest.

regards,

Manan

 

[artvvb]

What does your physical setup look like?

Here's an equivalent screenshot of me moving a 1V source from A0 to A1 and back several times with the modified code:

Thanks,

Arthur

[Manan Oza]

Thanks Arthur @artvvb

Physical setup is like this:

3V3 (yellow)attached to 220k Resister divider (5 Resister). Ground (orange) is connected to lower end of resister divider.

A0 (green) is connected to resister divider near Ground.

 

Thanks for your help.

 

regards,

Manan

[artvvb]

Hey @Manan Oza, sorry for the delay.

Your connections to the board look fine.

This might be, but probably isn't, some specific issue with Vivado 2021.2. One of my coworkers quickly tried out the project in it and has almost ruled it out.

A more likely theory: If the resistances of your resistors are too large, the input divider used to scale the single-ended pin voltages down from 0-3.3V to 0-1V could be forming a resistor divider with your network, and effectively pulling the analog input pin to ground. I've now tried the demo out with sets of three of: 5MOhm resistors (didn't light up, near-0 V reading in hardware manager), 20 kOhm resistors (didn't light up, 0.047V reading at the where it should be ~1.0V/3), and 6.8 Ohm resistors (3 leds lit up, 0.326V reading at the 1.0V/3 point). You can find more detail on the analog input circuitry in the analog input section of the reference manual: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual#shield_analog_io.

This wouldn't explain issues with the differential XADC inputs, or with measuring the 3.3V rail directly, if you are also seeing issues there.

Thanks,

Arthur

[Manan Oza]

Thanks Arthur @artvvb,

 

Thanks to your coworker and team too.

 

I tried with 18 Ohm and now it is working fine.

 

I really appreciate you and your team's hard work and zeal to solve the issue.

 

regards,

Manan

Edited February 9, 2023 by Manan Oza