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Found 8 results

  1. I am doing the implementation of a design in vivado at 25MHz frequency in Arty A7 100T fpga board, while doing that i am getting a critical warning that 2883 nets are not routed due to routing congestion even though i am setting the pblock utilization at 50% during floorplanning and the congestion report is not showing where the congestion is. So i am stuck with this design at implementation stage, can you guys suggest how to resolve this congestion. I am attaching the screenshot of the congestion report and the critical warning that came in the implementation log file. Thanks
  2. Hey, I am using Cortex M1 soft core processor on Arty A7 100T using Vivado 2020.1 and successfully generated bitstream for simple AXI-Uartlite project and exported hardware xsa file, but when i tried to create a Application Project for the same using xsa file in Vitis 2020.1 the platform is getting created but the basic c/c++ application project creation is giving error as "Failed to call GENERATE_APP". Below is the Vitis log file for that error. Can someone help in debugging this error? Thanks 13:51:28 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 13:51:28 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 13:51:28 INFO : Launching XSCT server: xsct.bat -n -interactive D:\FPGA_Projects\Workspace\temp_xsdb_launch_script.tcl 13:51:28 INFO : XSCT server has started successfully. 13:51:28 INFO : Registering command handlers for Vitis TCF services 13:51:29 INFO : plnx-install-location is set to '' 13:51:29 INFO : Successfully done setting XSCT server connection channel 13:51:29 INFO : Successfully done query RDI_DATADIR 13:51:29 INFO : Successfully done setting workspace for the tool. 13:51:29 INFO : Restoring global repository preferences: C:\Users\vybha\Documents\AT472-BU-98000-r0p1-00rel0\vivado\Arm_sw_repository 13:51:31 INFO : Platform repository initialization has completed. 13:52:35 INFO : Result from executing command 'getProjects': Microblaze_uart_wrapper;arty_uart1_wrapper;arty_uart_wrapper;arty_uart_wrapper_1;arty_uart_wrapper_2;cortex_m1_uart_wrapper;design_1_wrapper;mblz_uart_gpio_wrapper;mblz_uart_gpio_wrapper_1;mblz_uart_gpio_wrapper_2;zynq_uart_wrapper 13:52:35 INFO : Result from executing command 'getPlatforms': Microblaze_uart_wrapper|D:/FPGA_Projects/Workspace/Microblaze_uart_wrapper/export/Microblaze_uart_wrapper/Microblaze_uart_wrapper.xpfm;arty_uart1_wrapper|D:/FPGA_Projects/Workspace/arty_uart1_wrapper/export/arty_uart1_wrapper/arty_uart1_wrapper.xpfm;arty_uart_wrapper_1|D:/FPGA_Projects/Workspace/arty_uart_wrapper_1/export/arty_uart_wrapper_1/arty_uart_wrapper_1.xpfm;arty_uart_wrapper_2|D:/FPGA_Projects/Workspace/arty_uart_wrapper_2/export/arty_uart_wrapper_2/arty_uart_wrapper_2.xpfm;arty_uart_wrapper|D:/FPGA_Projects/Workspace/arty_uart_wrapper/export/arty_uart_wrapper/arty_uart_wrapper.xpfm;design_1_wrapper|D:/FPGA_Projects/Workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm;mblz_uart_gpio_wrapper_1|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_1/export/mblz_uart_gpio_wrapper_1/mblz_uart_gpio_wrapper_1.xpfm;mblz_uart_gpio_wrapper_2|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_2/export/mblz_uart_gpio_wrapper_2/mblz_uart_gpio_wrapper_2.xpfm;mblz_uart_gpio_wrapper|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper/export/mblz_uart_gpio_wrapper/mblz_uart_gpio_wrapper.xpfm;zynq_uart_wrapper|D:/FPGA_Projects/Workspace/zynq_uart_wrapper/export/zynq_uart_wrapper/zynq_uart_wrapper.xpfm 13:52:35 INFO : Platform 'cortex_m1_uart_wrapper' is added to custom repositories. 13:52:36 ERROR : Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. 13:52:36 ERROR : java.lang.RuntimeException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdk.xsdb.XsdbCommandUtils.handleResult(XsdbCommandUtils.java:387) at com.xilinx.sdk.xsdb.XsdbCommandUtils.executeAndRespond(XsdbCommandUtils.java:325) at com.xilinx.sdx.sdk.core.gen.CTemplateGen.generate(CTemplateGen.java:105) at com.xilinx.sdx.sdk.core.gen.CppTemplateGen.generate(CppTemplateGen.java:53) at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:93) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) 13:52:36 ERROR : Failed to create application project org.eclipse.core.runtime.CoreException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:150) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.executeInternal(SdkAppCreationHandler.java:75) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.lambda$1(SdkAppCreationHandler.java:67) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2311) 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references'
  3. Dear All, Board in use: ARTY A7-100T Flash in use: FL128SAIF00 Spansion Goal: to write 10 bytes of user data to flash and then read it later to use it in code. Present status : I am using microblaze , along with axi quad spi, mig , clock wizard, small PL logic etc. in my block design. I am able to program the flash and I am able sucessfully use bootloader to load the srec image from flash when the board powers up. So flash reading/ writing is working for this purpose. Now I want to simply write few bytes to flash and then read it from microblaze code. For this I followed a link found on this forum: https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilisf/examples/xilisf_spips_sst_polled_example.c?_ga=2.258985923.834060548.1609139438-288455063.1605863153 I made small changes to the code to suit my requirements and now it looks like this: #include "xparameters.h" /* EDK generated parameters */ //#include "xscugic.h" /* Interrupt controller device driver */ #include "xil_exception.h" #include "xil_printf.h" #include "xplatform_info.h" #include <xilisf.h> /************************** Constant Definitions *****************************/ /* * The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define SPI_DEVICE_ID XPAR_SPI_0_DEVICE_ID /* * The following constants define the offsets within a FlashBuffer data * type for each kind of data. Note that the read data offset is not the * same as the write data because the SPI driver is designed to allow full * duplex transfers such that the number of bytes received is the number * sent and received. */ #define DATA_OFFSET 4 /* Start of Data for Read/Write */ #define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and quad reads */ /* * The following constants specify the page size, sector size, and number of * pages and sectors for the FLASH. The page size specifies a max number of * bytes that can be written to the FLASH with a single transfer. */ #define SECTOR_SIZE 0x10 #define NUM_SECTORS 0x02 /* * Flash address to which data is to be written. */ #define TEST_ADDRESS 0x003D0D00 #define UNIQUE_VALUE 0x05 /* * The following constants specify the max amount of data and the size of the * the buffer required to hold the data and overhead to transfer the data to * and from the FLASH. */ #define MAX_DATA SECTOR_SIZE * NUM_SECTORS /* * The following constant defines the slave select signal that is used to * to select the FLASH device on the SPI bus, this signal is typically * connected to the chip select of the device */ #define FLASH_SPI_SELECT_1 0x01 #define FLASH_SPI_SELECT_0 0x00 /**************************** Type Definitions *******************************/ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Function Prototypes ******************************/ int FlashErase(XIsf *InstancePtr, u32 Address, u32 ByteCount); int FlashWrite(XIsf *InstancePtr, u32 Address, u32 ByteCount, u8 Command); int FlashRead(XIsf *InstancePtr, u32 Address, u32 ByteCount, u8 Command); int WriteEnable(XIsf *InstancePtr); int SpiFlashPolledExample(XSpi *SpiInstancePtr, u16 SpiDeviceId); /************************** Variable Definitions *****************************/ /* * The instances to support the device drivers are global such that they * are initialized to zero each time the program runs. They could be local * but should at least be static so they are zeroed. */ static XSpi SpiInstance; static XIsf Isf; /* * The following variables are used to read and write to the eeprom and they * are global to avoid having large buffers on the stack */ u8 ReadBuffer[MAX_DATA + DATA_OFFSET + DUMMY_SIZE]; u8 WriteBuffer[MAX_DATA + DATA_OFFSET]; u8 IsfWriteBuffer[XISF_CMD_SEND_EXTRA_BYTES + 1]; /*****************************************************************************/ /** * * Main function to call the SPI Flash example. * * @param None * * @return XST_SUCCESS if successful, otherwise XST_FAILURE. * * @note None * ******************************************************************************/ int main(void) { int Status = XST_FAILURE; xil_printf("SPI FLASH Polled Example Test \r\n"); /* * Run the Spi Interrupt example. */ Status = SpiFlashPolledExample(&SpiInstance,SPI_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("Status: %d \r\n", Status); xil_printf("SPI FLASH Polled Example Test Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran SPI FLASH Polled Example Test\r\n"); return XST_SUCCESS; } /***************************************************************************** * * The purpose of this function is to illustrate how to use the XSpiPs * device driver in interrupt mode. This function writes and reads data * from a serial FLASH. * * @param None. * * @return XST_SUCCESS if successful else XST_FAILURE. * * @note * * This function calls other functions which contain loops that may be infinite * if interrupts are not working such that it may not return. If the device * slave select is not correct and the device is not responding on bus it will * read a status of 0xFF for the status register as the bus is pulled up. * *****************************************************************************/ void FlashWriteSPI(XIsf *InstancePtr, u32 Address, u32 ByteCount, u8 Command); int SpiFlashPolledExample(XSpi *SpiInstancePtr, u16 SpiDeviceId) { xil_printf("Inside SPI Flash Polled Example\r\n"); u8 *BufferPtr; u8 UniqueValue; u32 Count; XSpi_Config *ConfigPtr; /* Pointer to Configuration ROM data */ u32 TempAddress; u32 MaxSize = MAX_DATA; u32 ChipSelect = FLASH_SPI_SELECT_1; if (XGetPlatform_Info() == XPLAT_MICROBLAZE) { MaxSize = 10 * 1; ChipSelect = FLASH_SPI_SELECT_0; /* Device is on CS 0 */ xil_printf("If 1 \r\n"); } /* * Lookup the device configuration in the temporary CROM table. Use this * configuration info down below when initializing this component. */ ConfigPtr = XSpi_LookupConfig(SpiDeviceId); if (ConfigPtr == NULL) { xil_printf("If 2 \r\n"); return XST_DEVICE_NOT_FOUND; } XSpi_CfgInitialize(SpiInstancePtr, ConfigPtr, ConfigPtr->BaseAddress); /* Initialize the XILISF Library */ XIsf_Initialize(&Isf, SpiInstancePtr, ChipSelect, IsfWriteBuffer); memset(WriteBuffer, 0x00, sizeof(WriteBuffer)); memset(ReadBuffer, 0x00, sizeof(ReadBuffer)); /* Unprotect Sectors */ FlashWrite(&Isf, 0, 0, XISF_WRITE_STATUS_REG); FlashErase(&Isf, TEST_ADDRESS, MaxSize); /* * Initialize the write buffer for a pattern to write to the FLASH * and the read buffer to zero so it can be verified after the read, the * test value that is added to the unique value allows the value to be * changed in a debug environment to guarantee */ TempAddress = TEST_ADDRESS; for (UniqueValue = UNIQUE_VALUE, Count = 0; Count < MaxSize; Count++, UniqueValue++, TempAddress++) { WriteBuffer[0] = (u8)(UniqueValue); FlashWrite(&Isf, TempAddress, 1, XISF_WRITE); xil_printf("Flash Write to %d, value is %d \r\n", TempAddress, WriteBuffer[0]); } /* * Read the contents of the FLASH from TEST_ADDRESS, using Normal Read * command */ FlashRead(&Isf, TEST_ADDRESS, MaxSize, XISF_READ); /* * Setup a pointer to the start of the data that was read into the read * buffer and verify the data read is the data that was written */ BufferPtr = &ReadBuffer[DATA_OFFSET]; for (UniqueValue = UNIQUE_VALUE, Count = 0; Count < MaxSize; Count++, UniqueValue++) { xil_printf("Flash Read is %d \r\n", BufferPtr[Count]); if (BufferPtr[Count] != (u8)(UniqueValue)) { //return XST_FAILURE; } } return XST_SUCCESS; } I edited only main and SpiFlashPolledExample function, all other functions are untouched. Now when I run it , I get (consoleOutput.png). I fear that flash is not being written at the first place. What am I missing here? Kindly help @D@n Any other working projects/examples would be of great help.
  4. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[1]}] set_property -dict {PACKAGE_PIN L18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[1]}] set_property -dict {PACKAGE_PIN M14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[0]}] set_property -dict {PACKAGE_PIN N14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[0]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[2]}] set_property -dict {PACKAGE_PIN M17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[2]}] set_property -dict {PACKAGE_PIN M18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[3]}] set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[3]}] This works great on S7. The problem comes in when trying to use my HDMI PMOD with my new Arty A7 board. I looked up the PMOD pins, and got // for the A7: // top row is D12, A11, B11, G13 // bot row is K16, A18, B18, D13 // so TMDS1 is {B11, G13} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {D12, A11} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {B18, D13} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {K16, A18} = {hdmi_out_n[3], hdmi_out_p[3]} and my constraints look like this set_property -dict { PACKAGE_PIN G13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[1] }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[1] }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[0] }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[0] }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[2] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[2] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[3] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[3] }]; #IO_25_15 Sch=ja[10] So as far as I can tell, I made sure that the same JA pins map to what the HDMI PMOD expects. All the RTL code is the same. But now I get these errors Not sure if this is one error causing another, or two different errors. First of all, it seems like the PMOD negative and positive pins are somehow swapped. Or at least that's how I am interpreting ”the positive port (P-side) of a differential pair cannot be placed on a negative package pin”. The other mystery is site IOB_X0Y149 not being part of a differential pair. Any help is appreciated, since this is my first foray into worrying about pin polarity
  5. Good afternoon. I was hoping to learn what the operation temperatures would be for the Arty A7-100 and the Arty A7-35. I am looking for a board that is able to withstand high temperatures (>40C) with some insulation. Thank you for your time
  6. I'm trying to build a design for the Arty A7-100 (not using MicroBlaze), using the AXI Quad SPI memory for user data (and also for bitstream storage). The Reference Manual (and the master .xdc file) mention six external pins for this (actually the .xdc file only mentions five). But when I select the Arty A7100/External Memory/Quad SPI Flash from the "Board" window, it gives me a block for which the SPI_0 interface has 18 pins. Essentially each data pin has become three (_i, _o and _t). Am I supposed to put IO buffers there myself, or have I somehow got the wrong block? If so, please would someone point me to the right package? Thanks
  7. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  8. elAmericano

    ESP32

    Hello, I am working on integrating ESP32 PMOD into a vivado 2018.2 project. I have imported DIgilent IP library into Vivado. When I place PMOD and connect to board, during compilation. It is actually a general message from the block design (See attached image). It apperas to me that this IP is for ArtyZ7? or some other Zync product? If so, is there IP available for Arty A7 or is this message to be ignored?