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Genesys 2 Board, DDR controller


Marv

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All:

      I'm trying to generate a DDR controller for the Genesys 2 board but I can't find a XDC file that show the FPGA-DDR pinout.  I saw a post to the forum that indicated that if the board configuration file was installed, the pinout would be filled in for you.  The board configuration file is installed, no pinout was displayed.  Can someone send me an XDC file (or segment of an XDC file) that shows the pin mapping to the DDR memories.  Thanks,

      Marv

 

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1 hour ago, Marv said:

All:

      I'm trying to generate a DDR controller for the Genesys 2 board but I can't find a XDC file that show the FPGA-DDR pinout.  I saw a post to the forum that indicated that if the board configuration file was installed, the pinout would be filled in for you.  The board configuration file is installed, no pinout was displayed.  Can someone send me an XDC file (or segment of an XDC file) that shows the pin mapping to the DDR memories.  Thanks,

      Marv

 

If you install the board files for that board, there is a MIG project inside. if you go with the IPI, you can simply drag the DDR component onto the diagram, and it will set everything up. Or you can download a MIG project file in DIgilent's github repository: https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys2/H

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The MIg IP creates it's own constraints from either a .ucf or .prj file, and it's pretty picky about syntax. For the HDL design flow I've generally had no luck with Mig .prj files but have been able to create usable .ucf files using those supplied by Digilent. The master .xdc file will not have any references to the DDR pins, though you need to have the signals on the port of your toplevel entity.

Personally, I don't use the IPI design flow and have found that, for recent versions of Vivado, specifying Genesys2 as the project device target causes all kinds of problems for me. I just select the proper Kintex device instead of the board option. Edited by zygot
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