Zybo-20 DDR3L

[Eran Zeavi]

Hello,

 

I am developing on Zybo-20 / zynq-7000 /xc7z020 . I am using the entire Vivado suite (HLS, Vivado, Vitis ) to write algorithm on the FPGA and application on the ARM processor (standalone , no OS).

I am struggling with running successfully even just simple examples provided online , using MAXI and AXI Stream interfaces, because the FPGA does not seem to be able to write onto the DDR3L 

I was wondering if my DDR settings are correct and maybe I am also missing DDR related configuration files to allow IP Core on PL  to write/read to/from it ?

Attached is a snapshot of the DDR3L setting out of the Zynq-7000 in Vivado

I am blocked now for few weeks and any help is appreciated !

 

Thanks !

Edited November 23, 2022 by Eran Zeavi

[artvvb]

Hi @Eran Zeavi

If you haven't already, you should install the board files for the Zybo Z7: Instructions are here.

The board files include a Zynq preset which is applied to the PS IP during Block Automation, which includes all of the relevant DDR configuration settings.

Which examples are you trying to use? In general for PL-to-DDR configuration, you will need some kind of DMA controller. The DMA Audio and HDMI demos for the Zybo Z7 implement several different Xilinx DMA IP, and include Zynq PS configurations.

Thanks,

Arthur