Eran Zeavi

Hi, i have successfully run other projects on that board, but w/o the use of the HDMI ports. I will look into your recommendation and keep you posted on my progress. Thanks !

Hi, I downloaded and built the HDNI example for the Zybo-20 from here : https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi Using Vitis IDE, I built it without issue; then programming the Zybo-20 board I get a memory write error at 0x10D000 below: Any help is welcome !

Hello, I am developing on Zybo-20 / zynq-7000 /xc7z020 . I am using the entire Vivado suite (HLS, Vivado, Vitis ) to write algorithm on the FPGA and application on the ARM processor (standalone , no OS). I am struggling with running successfully even just simple examples provided online , using MAXI and AXI Stream interfaces, because the FPGA does not seem to be able to write onto the DDR3L I was wondering if my DDR settings are correct and maybe I am also missing DDR related configuration files to allow IP Core on PL to write/read to/from it ? Attached is a snapshot of the DDR3L setting out of the Zynq-7000 in Vivado I am blocked now for few weeks and any help is appreciated ! Thanks !

Hi, I purchased the Zybo-20 few months ago I there a big road-block on my way every time I am programming the board even with very simple "hello Word" examples that can be found on github / Vitis , because of a consistent IMU error showed on the picture below. I am struggling with bringing up that board and move forward because of that issue. I am using the Stand Alone OS . I could not find any solution from the forums. Any help is welcome ! Thanks !

Hi, I am working on Zybo-20, trying to run a simple example to stream data from Zynq to the AXI Stream FIFO and back to Zynq The code example I am running on the ARM in StandAlone OS: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/llfifo/examples/xllfifo_polling_example.c the schematic is in the attachment. The issue is that when sending the data in TxSend, it waits for transmission complete forever in the loop below : /* Check for Transmission completion */ while( !(XLlFifo_IsTxDone(InstancePtr)) ){ } in other words, transmission never succeeds Any good idea is welcome ! Thanks !

is there a pre-built BSP for ZYBO-z7-20 ?

Hello, I am developing on Zybo-Z720 with Zynq XC7Z020-1CLG400C I am trying to boot Petalinux 2022.1 rootfs from SD card with a prebuilt image . I am using the BSP provided by XILINX here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html under section Zynq-7000 SoC Board Support Packages - 2022.1 , claimed to support ZC702 and I am really confused if it is a good match Is it indeed the right BSP to use ? if not is there one available ? After writing Petalinux with that BSP to my SD CARD and booting my board from it, I also installed Tera tem to comm with it through the UART/USB port @ 115600 bauds, but nothing seems to work and there is no HDMI output either. can you help ? Thank you

Thank you for the help ! I was just not not sure if the slight mismatch in the board name would make a difference

Hello, I installed the unified Vitis Vivado per the instructions here: https://digilent.com/reference/learn/programmable-logic/tutorials/zedboard-getting-started-with-zynq/start So far so good up to section 8. Launch SDK . This menu does not exist on Vivado 2022.1 I could not find documentation that would help me. Any idea ? Thanks ! Terence

Hi, Zybo Z7 - 20 has FPGA XC7Z020-1CLG400C. When I create a project with Vitis HLS in the device selection there are a few matching XC7Z020 but none with 1CLG400C Any idea how to overcome this ? Thank you