Eran Zeavi

Sounds good thanks !

not able to build any other project. I ll probably upgrade to windows 11 since it's working for you . A Windows 10 update may have killed my environment and would not be surprised ... Is Vivado working on VM too ? Ubuntu VM for instance ? Thank you though for the help !

yes, many times . It was all working until 3 weeks ago. I suspect windows/java or another environment thing I am not able to pinpoint the root cause Are you running Vivado on windows or linux ?

no error, just critical warnings on refclk and pixclk modules not found CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. INFO: [Timing 38-2] Deriving generated clocks [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2] WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of [get_ports -scoped_to_current_instance clk]'. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2] Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:2] CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:5] Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options [c:/Users/Terence/Vivado-2024/FPGA-Dev5/Zybo-Z7-20-HDMI-hw.xpr/Zybo-Z7-HW/Zybo-Z7-HW.gen/sources_1/bd/design_1/ip/design_1_v_tc_in_0/design_1_v_tc_in_0_clocks.xdc:6]

@artvvb just these critical warnings on the picture attached here . Synthesis did not complete

I am using the 2024 version of the demo with Vivado 2024 for Windows. The demo has been synthesizing and running just fine for months. Since 3 weeks ago, I am experiencing recurrent and random crashes of Vivado during "generate block design" and I have synthesis generating a blank "synthesized Design". Reinstalling Vivado-2024 for Windows from scratch did not help. Reverting last Windows updates did not help; reinstalling JAVA did not help. I have systematic Vivado crashes or failing synthesis at best. ila_pixclk message is a warning but synthesis fails. Not sure how to go from there ... Pictures attached to illustrate the issue. Thanks for the help !

@Boneoh The demo was running just fine for months. Since 3 weeks ago, I am experiencing recurrent and random crashes of Vivado during "generate block design" and I have synthesis generating a blank "synthesized Design". Reinstalling Vivado-2024 for Windows from scratch did not help. Reverting last Windows updates did not help; reinstalling JAVA did not help. I have systematic Vivado crashing or failing synthesis. Not sure how to go from there ... Are you running Vivado on Windows or Linux ? Thanks

Hi, There is a new recent issue (about a week ago) with the HDMI demo for zybo-20, after months it has been working for me. I reinstalled fresh Vivado and HDMI demo , not solving the issue. Vivado 2024.1 fails synthetising the project due to "ila_pixclk module not found" error showed on the picture. My guess is that the ILA IP upgrade killed it but not sure Any idea ? Thanks Eran

Hi, I have successfully synthesized , run implementation, generate bitstream and run the demo on the Zybo-20 for months. https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi?srsltid=AfmBOop9a-MucVEfknyx8HaKfWE7-R2OmdNU_QDW0KVyIGjC0MkbEdho Since 2 days ago, synthesis fails in Vivado 2023.2 with the following error: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file ......../Zybo-Z7-20-HDMI-hw.xpr/hw/hw.gen/sources_1/bd/design_1/ip/design_1_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module. Not sure what makes it suddenly fail consistently, maybe an IP update in ILA ? Any idea ? Thans Eran

Hi, in vga_modes.h you can find a list of all supported video formats. I have the same issue as you, I Iam software and embedded software developer, but my knowledge with video is limited. I am right now looking to downscale the frame rate from 60Hz down to 5 Hz t and still trying to figure it out. What is your project about ?

excellent ! thank you !

Hi, I am working on Zybo-20 / Zynq7 /xc7z020 FPGA and I was wondering if there is a soble filter kernel I can integrate in my Vivado project ? (like Zedboard has the LogixTronix one) Thank you! Eran

Hi, i have successfully run other projects on that board, but w/o the use of the HDMI ports. I will look into your recommendation and keep you posted on my progress. Thanks !

Hi, I downloaded and built the HDNI example for the Zybo-20 from here : https://digilent.com/reference/programmable-logic/zybo-z7/demos/hdmi Using Vitis IDE, I built it without issue; then programming the Zybo-20 board I get a memory write error at 0x10D000 below: Any help is welcome !

Hello, I am developing on Zybo-20 / zynq-7000 /xc7z020 . I am using the entire Vivado suite (HLS, Vivado, Vitis ) to write algorithm on the FPGA and application on the ARM processor (standalone , no OS). I am struggling with running successfully even just simple examples provided online , using MAXI and AXI Stream interfaces, because the FPGA does not seem to be able to write onto the DDR3L I was wondering if my DDR settings are correct and maybe I am also missing DDR related configuration files to allow IP Core on PL to write/read to/from it ? Attached is a snapshot of the DDR3L setting out of the Zynq-7000 in Vivado I am blocked now for few weeks and any help is appreciated ! Thanks !