Problem with HDF file generation

[sarvan]

Hi,

Recently we bought the Genesys ZU 5EV board. By using getting started guide link we tried experiment to build the vivado project to generate the HDF file. Below link we refer to down load the project.

https://github.com/Digilent/Genesys-ZU/tree/5ev/oob/master?_ga=2.41562411.885368752.1662031212-79180258.1662031212

https://github.com/Digilent/Genesys-ZU-HW/tree/5ev/master

We used the Vivado 2020.1 version.But we facing the issue(find in the attachment) when run the below command

source ../digilent-vivado-scripts/digilent_vivado_checkout.tcl

We required the XSA file to process further to build and generate the binaries using petalinux tool.

Could you please confirm  about the why the issue occurs in the vivado tool

Is there anything we missed?

can you share the HDF(XSA) file for the ZU5EV board?

It will be helpful us to proceed further.

 

Thanks

saravanan

 

[JColvin]

Hi @sarvan,

The error you are getting is indicating that you do not have the board files for the Genesys ZU installed (which tells Vivado how the UltraScale+ IP is configured). There is a guide on how to install the board files available here: https://digilent.com/reference/programmable-logic/guides/installing-vivado-and-vitis#install_digilent_s_board_files.

Thanks,
JColvin

 

[sarvan]

Hi @JColvin

 We tried with steps mentioned in the above link and the board files are added to the tool. We tried the same above steps to recreate and generate the *.xsa for the above project,but still we are facing same issue as the board part file is not supported.

Is there any thing we missed?

 

Thanks

saravanan

 

[sarvan]

Hi,

For genesys ZU5EV board, i created the simple block design to generate the Hardware Description file(XSA) for using in petalinux project to run configure command. When run the validate design showing error.

ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
/zynq_ultra_ps_e_0/saxihpc0_fpd_aclk

Find the block design below.

What are all IPs to be connected for genesys ZU5EV baord to generate the xsa file?

Is there any example block design available for the ZU5EV board?

 

Thanks

saravanan

 

 

[JColvin]

Hi @Saravanan,

You'll need to connect the saxihpc0_fpd_aclk to the same line as the maxihpm0_lpd_aclk port, or at least I have needed to do that for when creating designs for the Genesys ZU boards.

There are a couple of example projects for the Genesys ZU available in its Resource Center here: https://digilent.com/reference/programmable-logic/genesys-zu/start#example_projects.

Let me know if you have any questions.

Thanks,
JColvin

[sarvan]

Hi @JColvin

Thanks for the reply.

We tried with the above steps the error is resolved. With the generated xsa file configured the petalinux project, generated and copied the BOOT.bin,boot.scr and image.ub, rootfs.tar.gz file to the SD card with FAT32 and EXT4 partition. when power up the board there is no log message in display(connected in putty).

Tried to use the example project but in the project_info.tcl have the lines to set the board part property as like below.

set_property "board_part" "digilentinc.com:gzu_5ev:part0:1.0" $project_obj

while run the below command as mentioned in the getting started guide issue occurs as board part is not supported.

source ../digilent-vivado-scripts/digilent_vivado_checkout.tcl

 

Thanks

saravanan

[sarvan]

Hi @JColvin

We cloned this repository and We used the Vivado 2020.1 version to build the project.

https://github.com/Digilent/Genesys-ZU-HW/tree/5ev/master

We tried to generate the bit stream  but facing the in the sysnthesis level. 

The error is system_v_tpg_0.dcp file is not found

Attached the screen shot for you reference.

 

Your help is much appreciated.

 

Thanks,

saravanan

[BogdanVanca]

Hello @sarvan,

Xilinx has a revision number overflow issue with this IP. Check out this link: https://support.xilinx.com/s/article/76960?language=en_US  and see if it solves your problem.

[sarvan]

Hi @BogdanVanca

After including the patch the issue is resolved.

But we are facing the another issue during the bit stream generation.

Error log

ImplementationWrite Bitstream[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
system_i/v_hdmi_tx_ss_0/U0/v_hdmi_tx/inst (<encrypted cellview>)
system_i/v_hdmi_rx_ss_0/U0/v_hdmi_rx/inst (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

 

Your help is much appreciated.

 

Thanks,

saravanan

 

 

 

[Ionut]

Hi @sarvan,

The HDMI 1.4/2.0 TX Subsystem and the HDMI 1.4/2.0 RX Subsystem IPs need purchased licenses to be able to compile bitstreams.

Alternatively, there might be evaluation licenses available, but you would need to check with Xilinx if they are available.

Please see the "Licensing and Ordering Information" section from the following Xilinx documents for details:

https://docs.xilinx.com/r/3.1-English/pg236-v-hdmi-rx-ss/Licensing-and-Ordering-Information

https://docs.xilinx.com/r/3.1-English/pg235-v-hdmi-tx-ss/Licensing-and-Ordering-Information

If such licenses are not available, you would need to remove the v_hdmi_tx_ss_0 and v_hdmi_rx_ss_0 IPs from the block design.

 

Best Regards!