to define the FPGA architecture. However, when I attempt to write to the DACs, I can only access one channel of the DAC at a time. I cannot access both channels simultaneously. The AD9717 datasheet clearly states that the input interface uses a DDR protocol. Is this something the provided hardware can do, or am I required to modify the blocks to produce simultaneous outputs.
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Udayan Mallik
@artvvb I am using an Eclypse Z7 with a DAC1411 and an ADC1410 to implement a control algorithm. I followed the instruction in https://www.hackster.io/whitney-knitter/hello-zmods-on-the-eclypse-z7-99107d
to define the FPGA architecture. However, when I attempt to write to the DACs, I can only access one channel of the DAC at a time. I cannot access both channels simultaneously. The AD9717 datasheet clearly states that the input interface uses a DDR protocol. Is this something the provided hardware can do, or am I required to modify the blocks to produce simultaneous outputs.
Udayan Mallik
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