Microblaze use of QSPI NOR Flash as Main Memory - on Cora S7

[mjdbishop]

Is there a reference example or cookery for using the Macronix QSPI flash as main memory for a Microblaze; e.g. on the CoraS7 which has neither DDR nor SRAM and limited BRAM - the C libraries will easily fill 256+ kBy of memory, the S7-25 has 80 BRAM blocks IIRC (320 kBy).

Narrowly the issue is how do you configure Microblaze + cache + QSPI flash (as Mb memory)

I can't find an answer ...

Martin

[JColvin]

Hi @mjdbishop,

I am working on creating a clean answer for you; I know there is a small similar guide by another Forum user here, https://forum.digilent.com/topic/22613-cmod-a7-doesnt-boot-sdk-code/, but I haven't specifically gone through that for the Cmod S7 (or at least I presume you mean Cmod rather than Cora since the Cora board sold by Digilent only has Zynq chips and does have DDR memory).

Thanks,
JColvin

 

[mjdbishop]

Hi @JColvin

Thank you for picking this issue up, and yes the target is the Cmod S7.  Any board with DDR or SRAM or even a Zynq's OCM is unlikely to require this QSPI use case.

The thread you link looks a bit frayed, and it only addresses the trivial requirement of boot loading - which I believe is fairly well documented, see e.g. from today https://app.livestorm.co/adiuvo-engineering/mastering-microblaze/live?s=5478d071-d14e-4aba-bb64-1b3891de5c27#/chat

My desire is to use the QSPI as main / backing memory for a microblaze + cache system, to enable non trivial micro blaze applications on the Cmod S7 platform.

My experience is that BRAM provides scarcely sufficient memory for a non-trivial C command line application; IIRC the S7-25 has 80 BRAMs which is 320 kBy, shave some off for data path FIFOs and you have no more than 256kBy for microblaze memory.  Similar to PDP 11/40 memory size; circa 1970.  The libraries and applications have bloated since then.

If the QSPI can't support the Mb + cache + QSPI concept I shall have to use a different processor core or a much simpler application (and smaller memory requirement).

I look forward to your response

Best Regards

Martin

PS Without this technique or an equivalent enabler, it is hard to see how the Cmod S7 can be used for non-trivial "processor" applications

[mjdbishop]

Hi @JColvin

An additional link found on my travels:

https://www.adiuvoengineering.com/whitepapers/microblaze-booting-from-qspi  which addresses the boot (to DDR) requirement

And for the avoidance of doubt, I'm anticipating the QSPI memory is used for immutable (primarily) code storage with an instruction cache to minimise latency and avert microblaze stalls, the mutable data memory would of course be in BRAM.

Best Regards

Martin