Pmod issue

[OscarW]

Hello,

I am using a pmod gps module and corresponding IP in vivado on a zedboard. My project uses the pps pulse generated by the gps module for timing and internal sync not very relevant to the question. But I also want to connect the IP, is there any way of branching the signal from the auto generated interface made by the board specification? If not, as mentioned in this thread from 2018, making ports manually through the contraints file and paring those to pin pmod_out_pin(1-4)_t? I get errors when leaving pmod_out_pinX_o and _i not connected, should these be shorted to the _t pin/ground/vcc?

 

[artvvb]

Hi @OscarW, welcome to the forum,

Unfortunately there isn't a good way of doing this with the board interface, since connecting anything to the pins in the interface will override the connection of that pin to the external port. All three of the i/o/t pins associated with a pmod pin get connected to one IO buffer. If you look at the HDL wrapper's port map, you can see that these three pins are merged into a single "_io" port that is the thing that gets a location constraint applied to it. Additionally, making the entire interface external doesn't solve the issue, since you still wouldn't be able to split out any particular pin. Expanding the interface to make all three of the individual pins you care about external doesn't automatically put in the required I/O buffer, and creates a set of three ports in the wrapper instead of the needed single inout port.

I would try to go about solving it by writing an RTL module which can sit in front of the GPS IP that handles instantiating the necessary tristate IOBUFs. You will also need to constrain this module's ports the manual way. I've attached an RTL module, below, which might give a decent start at this, but please note that I've only checked it by validating a block design and not by actually generating a bitstream.

I've also attached a screenshot of how it would be wired up in a BD, the Pmod bridge is a stand-in for your Pmod GPS, as is the (empty) "other_logic" module.

Thanks,

Arthur

 

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 06/21/2022 11:31:12 AM
// Design Name: 
// Module Name: pmod_breakout
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pmod_breakout(
    inout pmod_ext_j1_io,
    inout pmod_ext_j2_io,
    inout pmod_ext_j3_io,
    inout pmod_ext_j4_io,
    inout pmod_ext_j7_io,
    inout pmod_ext_j8_io,
    inout pmod_ext_j9_io,
    inout pmod_ext_j10_io,
    
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN1_I" *)
    output pmod_int_j1_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN2_I" *)
    output pmod_int_j2_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN3_I" *)
    output pmod_int_j3_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN4_I" *)
    output pmod_int_j4_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN7_I" *)
    output pmod_int_j7_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN8_I" *)
    output pmod_int_j8_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN9_I" *)
    output pmod_int_j9_i,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN10_I" *)
    output pmod_int_j10_i,
    
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN1_O" *)
    input pmod_int_j1_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN2_O" *)
    input pmod_int_j2_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN3_O" *)
    input pmod_int_j3_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN4_O" *)
    input pmod_int_j4_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN7_O" *)
    input pmod_int_j7_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN8_O" *)
    input pmod_int_j8_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN9_O" *)
    input pmod_int_j9_o,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN10_O" *)
    input pmod_int_j10_o,
    
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN1_T" *)
    input pmod_int_j1_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN2_T" *)
    input pmod_int_j2_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN3_T" *)
    input pmod_int_j3_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN4_T" *)
    input pmod_int_j4_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN7_T" *)
    input pmod_int_j7_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN8_T" *)
    input pmod_int_j8_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN9_T" *)
    input pmod_int_j9_t,
    (* X_INTERFACE_INFO = "digilentinc.com:interface:pmod_rtl:1.0 pmod_int PIN10_T" *)
    input pmod_int_j10_t,
    
    output [7:0] pmod_pins
);
    assign pmod_pins = {
        pmod_ext_j10_io,
        pmod_ext_j9_io,
        pmod_ext_j8_io,
        pmod_ext_j7_io,
        pmod_ext_j4_io,
        pmod_ext_j3_io,
        pmod_ext_j2_io,
        pmod_ext_j1_io
    };

    IOBUF j1_inst (
        .O(pmod_int_j1_i),     // Buffer output
        .IO(pmod_ext_j1),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j1_o),     // Buffer input
        .T(pmod_int_j1_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j2_inst (
        .O(pmod_int_j2_i),     // Buffer output
        .IO(pmod_ext_j2),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j2_o),     // Buffer input
        .T(pmod_int_j2_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j3_inst (
        .O(pmod_int_j3_i),     // Buffer output
        .IO(pmod_ext_j3),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j3_i),     // Buffer input
        .T(pmod_int_j3_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j4_inst (
        .O(pmod_int_j4_i),     // Buffer output
        .IO(pmod_ext_j4),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j4_o),     // Buffer input
        .T(pmod_int_j4_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j7_inst (
        .O(pmod_int_j7_i),     // Buffer output
        .IO(pmod_ext_j7),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j7_i),     // Buffer input
        .T(pmod_int_j7_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j8_inst (
        .O(pmod_int_j8_i),     // Buffer output
        .IO(pmod_ext_j8),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j8_o),     // Buffer input
        .T(pmod_int_j8_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j9_inst (
        .O(pmod_int_j9_i),     // Buffer output
        .IO(pmod_ext_j9),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j9_i),     // Buffer input
        .T(pmod_int_j9_t)      // 3-state enable input, high=input, low=output
    );
    IOBUF j10_inst (
        .O(pmod_int_j10_i),     // Buffer output
        .IO(pmod_ext_j10),   // Buffer inout port (connect directly to top-level port)
        .I(pmod_int_j10_o),     // Buffer input
        .T(pmod_int_j10_t)      // 3-state enable input, high=input, low=output
    );
endmodule

 

[Richm]

Do you have the IP source code?

If so, add an output port and assign it the input you want to use elsewhere. Simple & easy.