I am working with a custom-made FMC (HPC) that attaches to a Genesys2 board with VADJ=3.3V. Among various signals, I have two LVDS_25 clock inputs on the pairs L25/K25 (FMC pins K4/K5) and F12/E13 (FMC pins K28/K29):
To my understanding, both pin pairs are clock-capable and Vivado synthesizes/implements without issues. The HB bank is powered by an external voltage of 3.3V from the FMC card.
For sanity checking, I pass both clocks through IBUFGDSs...
...divide the clock and power a couple of LEDs to confirm signal availability:
reg [25:0] r_clk0div = 0;
reg [25:0] r_clk1div = 0;
assign led[0] = r_clk0div[25];
assign led[1] = r_clk1div[25];
always @(posedge w_clk0_ibufg) begin
r_clk0div <= r_clk0div + 1;
end
always @(posedge w_clk1_ibufg) begin
r_clk1div <= r_clk1div + 1;
end
To my surprise, I see only led[0] blinking (with irregularities), but not led[1]. I see a LVDS signal on the FMC connector pins of both clock inputs. The signals are somewhat distorted (oscilloscope struggles to trigger at the proper period) and led[0] blinks irregularly at times.
Due to reasons, the FMC is connected to the Genesys2 board by an 250mm cable [1]. My guess is that the additional connector introduces reflections and the cable attenuates the clock signals to a degree that the FPGA does not detect a LVDS signal. Is it really this "simple", or am I missing something?
Question
tido
I am working with a custom-made FMC (HPC) that attaches to a Genesys2 board with VADJ=3.3V. Among various signals, I have two LVDS_25 clock inputs on the pairs L25/K25 (FMC pins K4/K5) and F12/E13 (FMC pins K28/K29):
To my understanding, both pin pairs are clock-capable and Vivado synthesizes/implements without issues. The HB bank is powered by an external voltage of 3.3V from the FMC card.
For sanity checking, I pass both clocks through IBUFGDSs...
...divide the clock and power a couple of LEDs to confirm signal availability:
To my surprise, I see only led[0] blinking (with irregularities), but not led[1]. I see a LVDS signal on the FMC connector pins of both clock inputs. The signals are somewhat distorted (oscilloscope struggles to trigger at the proper period) and led[0] blinks irregularly at times.
Due to reasons, the FMC is connected to the Genesys2 board by an 250mm cable [1]. My guess is that the additional connector introduces reflections and the cable attenuates the clock signals to a degree that the FPGA does not detect a LVDS signal. Is it really this "simple", or am I missing something?
[1] https://www.mouser.ca/ProductDetail/200-HDR-169468-01
Edited by tidoadd details
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