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Found 5 results

  1. I use Xilinx Spartan3E chip to design a SDRAM data storage module, I put the global clock through ODDR2 to output a clock to the SDRAM for data reading, writing and sampling, but I found that I output this clock 80M when the voltage swing is only 500mV, the higher the frequency, the smaller the voltage swing. And I want to push the SDRAM clock to 140M, how to solve this problem? FPGA operating conditions: BANK voltage: 3.3V
  2. In the board description for the ArtyS7, it's written to have a 12 MHz system clock at pin F14. That's not correct. Schematic revision E.1 for ArtyS7 is showing IC2 is open => no clock at all IC2 is - if soldered - a 100 MHz clock => ASEM1-100.000MHZ-LC-T As also discovered by the author of the board description, 12 MHz is a useless clock for 7-series FPGA,s because it's to slow for clock modifying blocks (PLL, MMCM, ...) The trace 12MHz/UCLK has a R0, but no source in schematics (incomplete schematics or an open trace ...) As a summary: the ArtyS7 board has officially no system clock, only DDR3 reference clock can be used.
  3. I'm learning how to generate clocks with XDC files, using the .xdc from the Basys 3 github repository as a starting point. I'd like to change the clock to a very low frequency of 1 Hz, or once per second, so that a LED blinks on and off once a second. The portion of the .xdc file that generates the clock looks like this: ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 1000000000.00 [get_ports clk] And the code for blinking the LED looks like this: module oneclock ( input clk, output led[15:0] ); assign led[0] = clk; endmodule I can synthesize, etc but the LED appears constantly lit, although dimmer than normal if I'm not mistaken. Is there a minimum to the generated clock? Apologies for the newbie question, any documentation or things to help me learn would be greatly appreciated.
  4. Hello, my name is Caleb. I am a senior electrical engineering student at Northern Illinois University. I am using the Analog Discovery 2 in order to capture analog pixels sent from a sensor at 5MHz and then interpreting that data on the Raspberry Pi 4. I am running into questions with the timing of the logging function of the oscilloscope on the Analog Discovery. I have noticed that when I send multiple acquisitions at once I run into issues with the timing on the next acquisition. It seems that each acquisition comes in order, but there is a delay between the end of one and the beginning of the next. For example, the time from the first sample to the last would be about 1.6 ms elapsed time. However the next acquisition would have a DateTime listed that is 50 ms later than the previous aquisition. My current settings I have been using are: Scope mode - Repeated Buffer: 10 (Not sure from the source material how this impacts acquisitions..) Logging Execute: Each acquisition 8192 samples Is there a way to have the acquisitions send the data out so that the end of acq0000 would correspond to the data at the beginning of acq0001? An additional question I have is how the AD2 Date Time function is working in the csv files exported as acquisitions. Is it a real time clock on the AD2 or is it information pulled from the pc/rpi? Thank you for any help you are able to provide on this. I can provide further information if it is needed.
  5. Hi there! I'm trying to make differential clock(100MHz from oscillator) to differential clock output(40MHz differential) clk_100M_P&M is connected to external crystal oscillator(input) and I allocated clk_40_P&M to PIO port(output). clk_front , clk_back is for check point. when I checked, the result was : clk_front : 100MHz & clk_back : 40MHz . However, clk_40_P &N port didn't output some waveform. I have no idea what's the problem. 1st trial : clk_front & back : LVCmos33 and clk_40_P & N : LVDS25 -> result : LVCmos33,(bank34) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) 2nd trial : clk_front & back : LVCmos25 and clk_40_P & N : LVDS25 -> result : LVCmos25 ,(bank35) clk_front & back (success) and (bank35) clk_40_P & N : LVDS25 ( failed ) thank you for your help!