Looking for step-by-step to set up microblaze with SPI bootloader on Arty A7 using Vitis

[DougM]

Hello,

I've got myself in a bit of a tangle in my attempts to get a configuration and microblaze app to load from SPI flash on power up. I'm new to Vivado, so there's a bit of a learning curve, for sure. 

I would love to find a step-by-step guide that not only explains *what* to do, but *why*. Though, at this point, I'd be happy to start with the direct what-to-do.

Right now, I have a configuration and simple microblaze program that I can program from Vitis, and all is well. I'm struggling with adding a bootloader application. I'm getting errors with the bootloader overflowing the amount of memory available, even though I've increased the Microblaze's local memory to 32K. But, really, I'm in a bit of a tangle with platforms, applications, systems etc etc.

At this point, I'd really like to scrape everything off and make a nice tidy fresh start... 

Any pointers are appreciated. I have found some guides, but they're mostly pre-Vitis and I may be making some mistake in translation. I'm using Vitis 2020.1. 

Regards

Doug

[DougM]

Well, I've got this working (mostly). I found the following guides quite helpful.

https://shadowcode.io/microblaze-srec-spi-bootloader-hardware/

https://shadowcode.io/vitis-srec-spi-bootloader-software/

I still don't have the system booting without help on power-up. I have to press the "prog button" but the configuration and app are loading and running correctly. That's the next thing to track down.

cheers

doug

 

[DougM]

Anyone??

[JColvin]

Hi @DougM,

I've personally never gotten the bootloader application process to work with Microblaze no matter what guide (Digilent, Xilinx, etc) to work on any version of Vivado, at least in recent years; Zynq based SPI flash applications work for me, though that's not relevant here since it's a different architecture.  I have vague recollections of having successfully done it once upon a time and having seen co-workers successfully do it, but have not been able to replicate that since then.
The general idea "why" aspect with regards to individual steps (as I understand it) is to set a particular region in the SPI flash associated with the bootloader. This will will configure the FPGA with its hardware configuration data and then tell the device to jump to a new address space in the SPI flash to then "initiate" the Microblaze application. Each region needs to be of a large enough size to hold the hardware configuration + instructions to go to the Microblaze application material, and then application itself. Since the hardware configuration size will change based on whatever you designed in Vivado and the application will be of its own size as well. Usually, there is some push to only assign as much space in the SPI flash as needed for each region because the SPI flash is much smaller in size compared to the DDR (or whatever) the application will actually be running in on the hardware.

In terms of getting an actual answer to you, the successful SPI flash application approach with Microblaze that I have used is to create a .elf file on the software side of the design and then go back into Vivado and associate the .elf file with Microblaze, which effectively puts the Microblaze application into BRAM. You are then able to have Vivado generate a .bin file which gets put into flash memory and have your application boot up from flash. This process is described more in this Forum thread here:

Please let me know if you have any questions.

Thanks,
JColvin

[DougM]

Hi JColvin,

Thanks for the reply. I *think* I understand how it's supposed to work, but so far I've not got the tools to make it happen...  I've got to the point where I believe the hardware configuration loads from the flash, as proven by the LEDs lighting up in a pattern I set up in the hardware design. But, the Microblaze app doesn't run.

I'll read the Forum thread you're suggesting. Thanks.

In general, though, if Xilinx is not really being very keen to support applications like this, maybe I should be looking at other approaches, such as Zynq. I'd rather stay on the main "thoroughfare" rather than explore the back streets...

Doug

[Richm]

What device?

If you already have processors onboard, the simplest is to use them. I think that the Vitis bootloader is for hard processors? Vitis works with a somewhat complicated platform/domain/system/app structure and the system level is for grouping all the apps that are intended to run concurrently on the chip. Building the system will create a boot file that contains the fpga bitstream, the elf files for all the processors, the fsbl and possibly the pmufw and ssbl. With a microblaze, doesn't the elf file need to included in the bitstream so that the instruction memory is loaded with the bitstream? This would mean Vivado -> Vitis -> Vivado to include the elf in the bitstream.

I'm not sure Xilinx really cares too much about "the little guy", altho I can tell you from experience that the more you use the software the easier it becomes.

[DougM]

Hi Richm

It's an Arty A7 board I'm using (hidden in the original post's title :)  ), so I'd be implementing a Microblaze to get a processor. I do have the processor working, and I can get the FPGA configuration to load from flash when the board powers up, so I feel I'm close. 

JColvin's suggestion is also Vivado->Vitis->Vivado but, so far, I haven't got that working. 

I have experience of programming a board (Kintex 7) set up by another engineer, using an older version of the tools. In that system he creates two .mcs files, one for the FPGA configuration which includes a Microblaze, and one for the Microblaze app. I think the first .mcs file contains the bootloader that knows where to find the Microblaze app in the flash. I'll have to track him down and have him explain it to me. His explanation of how that goes together might be informative.

Thx, Doug

[DougM]

And so, finally, it seems the board will boot without help if I apply power without it being plugged into the PC that's running Vivado/Vitis...

doug

[JColvin]

Hi @DougM,

I'll have to try out this guide you linked and see if I can have a successful experience with the SREC bootloader since you were able to get it working.

As for successfully booting when plugged into a different power source, my guess (as opposed to confirmation) is that there is something in the JTAG configuration that automatically happens when the board is plugged in and Vivado/Vitis/other Xilinx software is opened that somehow prevents the board from booting without manually pushing the PROG button. If this guess is true, then I would expect that if you programmed the flash memory and then closed out Vivado/Vitis, the board boot from flash on power-up when connected to that same computer.

Thanks,
JColvin

[DougM]

Hi JColvin,

Yes, I think your conjecture is correct. It's only Vivado that must be closed for the board to boot, so I suppose something in the hardware manager system is talking to the board.

Now, I'm going to try to get the board to configure and load the application more quickly. It takes about 7 seconds to configure, which seems excessively slow. I think I may have the SPI bus width wrong because when I try to create an MCS file the system complains that the bit file is configured for SPIx1 not x4.  This is odd, because the block design is clearly x4. Somewhere, something is goofed up. 

I think my brain must have different defaults than the designers of the user interface... I'm finding it quite hard to track things down!

thanks,
doug

[DougM]

All is now working as expected. I, eventually, found how to properly configure SPIx4 at 50MHz and the board configures very quickly. 

For my next adventure, I may try to see if I can do the same thing with Vivado/Vitis 2022.  I believe the SPI library is handled differently. Any pointers?

Thx, Doug

[JColvin]

Hi @DougM,

Not a direct example no. The main thing that I am curious about (but have not directly looked into) is to see if Xilinx's own built in SREC Bootloader example has made the switch over from the now depreciated xilisf library to the (Xilinx) SPI library.

Based on this Xilinx article, https://support.xilinx.com/s/article/73329?language=en_US, it would seem that most of the functions offered by the xilisf library have been consolidated into single functions (like the transfer, erase, read, write, GetDeviceInfo, WriteEnable, etc.; all have their functionality achieved through XSpi_Transfer), leaving a lot of the specific functionality up to the end user. In theory, it would be a straightforward port of library functions, albeit time consuming, but I do not know if Xilinx has done this for their own examples.

Everything on the Digilent side of things in terms of following the tutorial you linked should be good to go since we don't directly use the depreciated xilisf library as far as I know.

Thanks,
JColvin

[DougM]

Hi JColvin,

Well, while it was all fresh in my mind  I tried to replicate my example using Vivado/Vitis 2021.2.  I gave up after it became clear that the hardware manager in that version is unusably slow with the Arty. This appears to be a bug in the HW manager, as evidenced by a google search.  I did not have the enthusiasm/time/real need to spend time on trying to figure out a work-around, or to install yet another version of Vivado. 

Thx,
Doug