Why am i getting 'Z' for the unused bit in the BRAM address port ?

[Vybhav MN]

Hey Everyone,

 

I am designing a project in which i used a custom soft core and LMB Bus, LMB Controller followed by Dual port BRAM for Data and instruction read write operations , The custom soft core is WORD ALIGNED.

 

The problem is that during the post implementation functional simulation the 32 bit Word aligned address that i am sending to the bram memory, the unused bits in the address port of BRAM is considered as 'Z' and hence when i dump the code in the FPGA the address is different(for eg. if i give address as 8000, 8004 its considering it as 2000,2001). The address port of FPGA is observed using ILA core. Hence i am not able to read the memory content form correct location.

 

i found a clue to solving this one in LMB controller which is that the LMB controller masks the unused bits to 'Z' in the address for access to LMB. But if i override the masking as manual and setting it to FFFFFFFF int IP customization, the design is still giving 'Z' for the unused address bits.

 

how can i overcome this problem?

 

Below are the screenshots for the reference

 

Thanks