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Vybhav MN

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  1. Hey Everyone, I am designing a project in which i used a custom soft core and LMB Bus, LMB Controller followed by Dual port BRAM for Data and instruction read write operations , The custom soft core is WORD ALIGNED. The problem is that during the post implementation functional simulation the 32 bit Word aligned address that i am sending to the bram memory, the unused bits in the address port of BRAM is considered as 'Z' and hence when i dump the code in the FPGA the address is different(for eg. if i give address as 8000, 8004 its considering it as 2000,2001). The address port of FPGA is observed using ILA core. Hence i am not able to read the memory content form correct location. i found a clue to solving this one in LMB controller which is that the LMB controller masks the unused bits to 'Z' in the address for access to LMB. But if i override the masking as manual and setting it to FFFFFFFF int IP customization, the design is still giving 'Z' for the unused address bits. how can i overcome this problem? Below are the screenshots for the reference Thanks
  2. Hey i got the mistake that was in the constraint file. The create clock command itself was not executing hence the was not created and all those timing and routing violations happened due to that. In the log this was just an info not even warning or an error so i didn't noticed that mistake and yeah i removed all those unnecessary constraints and kept just the create clock and pins one.
  3. I am doing the implementation of a design in vivado at 25MHz frequency in Arty A7 100T fpga board, while doing that i am getting a critical warning that 2883 nets are not routed due to routing congestion even though i am setting the pblock utilization at 50% during floorplanning and the congestion report is not showing where the congestion is. So i am stuck with this design at implementation stage, can you guys suggest how to resolve this congestion. I am attaching the screenshot of the congestion report and the critical warning that came in the implementation log file. Thanks
  4. Hey, I am using Cortex M1 soft core processor on Arty A7 100T using Vivado 2020.1 and successfully generated bitstream for simple AXI-Uartlite project and exported hardware xsa file, but when i tried to create a Application Project for the same using xsa file in Vitis 2020.1 the platform is getting created but the basic c/c++ application project creation is giving error as "Failed to call GENERATE_APP". Below is the Vitis log file for that error. Can someone help in debugging this error? Thanks 13:51:28 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 13:51:28 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 13:51:28 INFO : Launching XSCT server: xsct.bat -n -interactive D:\FPGA_Projects\Workspace\temp_xsdb_launch_script.tcl 13:51:28 INFO : XSCT server has started successfully. 13:51:28 INFO : Registering command handlers for Vitis TCF services 13:51:29 INFO : plnx-install-location is set to '' 13:51:29 INFO : Successfully done setting XSCT server connection channel 13:51:29 INFO : Successfully done query RDI_DATADIR 13:51:29 INFO : Successfully done setting workspace for the tool. 13:51:29 INFO : Restoring global repository preferences: C:\Users\vybha\Documents\AT472-BU-98000-r0p1-00rel0\vivado\Arm_sw_repository 13:51:31 INFO : Platform repository initialization has completed. 13:52:35 INFO : Result from executing command 'getProjects': Microblaze_uart_wrapper;arty_uart1_wrapper;arty_uart_wrapper;arty_uart_wrapper_1;arty_uart_wrapper_2;cortex_m1_uart_wrapper;design_1_wrapper;mblz_uart_gpio_wrapper;mblz_uart_gpio_wrapper_1;mblz_uart_gpio_wrapper_2;zynq_uart_wrapper 13:52:35 INFO : Result from executing command 'getPlatforms': Microblaze_uart_wrapper|D:/FPGA_Projects/Workspace/Microblaze_uart_wrapper/export/Microblaze_uart_wrapper/Microblaze_uart_wrapper.xpfm;arty_uart1_wrapper|D:/FPGA_Projects/Workspace/arty_uart1_wrapper/export/arty_uart1_wrapper/arty_uart1_wrapper.xpfm;arty_uart_wrapper_1|D:/FPGA_Projects/Workspace/arty_uart_wrapper_1/export/arty_uart_wrapper_1/arty_uart_wrapper_1.xpfm;arty_uart_wrapper_2|D:/FPGA_Projects/Workspace/arty_uart_wrapper_2/export/arty_uart_wrapper_2/arty_uart_wrapper_2.xpfm;arty_uart_wrapper|D:/FPGA_Projects/Workspace/arty_uart_wrapper/export/arty_uart_wrapper/arty_uart_wrapper.xpfm;design_1_wrapper|D:/FPGA_Projects/Workspace/design_1_wrapper/export/design_1_wrapper/design_1_wrapper.xpfm;mblz_uart_gpio_wrapper_1|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_1/export/mblz_uart_gpio_wrapper_1/mblz_uart_gpio_wrapper_1.xpfm;mblz_uart_gpio_wrapper_2|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper_2/export/mblz_uart_gpio_wrapper_2/mblz_uart_gpio_wrapper_2.xpfm;mblz_uart_gpio_wrapper|D:/FPGA_Projects/Workspace/mblz_uart_gpio_wrapper/export/mblz_uart_gpio_wrapper/mblz_uart_gpio_wrapper.xpfm;zynq_uart_wrapper|D:/FPGA_Projects/Workspace/zynq_uart_wrapper/export/zynq_uart_wrapper/zynq_uart_wrapper.xpfm 13:52:35 INFO : Platform 'cortex_m1_uart_wrapper' is added to custom repositories. 13:52:36 ERROR : Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. 13:52:36 ERROR : java.lang.RuntimeException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdk.xsdb.XsdbCommandUtils.handleResult(XsdbCommandUtils.java:387) at com.xilinx.sdk.xsdb.XsdbCommandUtils.executeAndRespond(XsdbCommandUtils.java:325) at com.xilinx.sdx.sdk.core.gen.CTemplateGen.generate(CTemplateGen.java:105) at com.xilinx.sdx.sdk.core.gen.CppTemplateGen.generate(CppTemplateGen.java:53) at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:93) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) 13:52:36 ERROR : Failed to create application project org.eclipse.core.runtime.CoreException: Failed to call GENERATE_APP Reason: ERROR: [Common 17-39] 'hsi::generate_app' failed due to earlier errors. at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:150) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79) at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.executeInternal(SdkAppCreationHandler.java:75) at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.lambda$1(SdkAppCreationHandler.java:67) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289) at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2311) 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references' 13:52:37 ERROR : An unexpected exception occurred in the module 'updating project references'
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