logical ports have no user assigned specific location constraint

[Guru Tim]

I am curious about this error and realise I can just remove it by changing some rules.
I have read various posts on the topic but not been able to resolve it.

I have a Zybo Z7-20 and have susceefully run a blink test using the IP Block to add my RTL and a clock wizard.
I then went on to create a more complex application, tested it under simulation and inserted it into the block in the same mannor as had worked with blink.

My constraints are applied to the pins I am using. What am I overlooking?

##Clock signal
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];

##LEDs
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led_0 }]; #IO_L23P_T3_35 Sch=led[0]
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led_1 }]; #IO_L23N_T3_35 Sch=led[1]

QUESTION: What is the #IO... on each line for? Is it just a comment or does it do something?

 

module WS2812B_64_LED_Driver(

    input  [23:0] dataIn,
    output  serialOut,
    output  clearToSend,
    input  clk_50ns, //20Mhz
    input reset
);

    // timing values in nanoseconds
    localparam    [5:0] t_clk = 50; // clock period ns
    localparam    [4:0] t_period = 1250 / t_clk; // 1 bit period ns
    localparam    [4:0] t_hi = 400 / t_clk; // hi bit period ns
    localparam    [4:0] t_lo = 800 / t_clk; // low bit period ns
    localparam    [9:0] t_reset = 50000 / t_clk; // reset period ns

    // LED's and bit tracking
    localparam    [6:0] led_count = 64; // number of WS2812 LED's in the string     
    localparam    [5:0] bit_count = 24; // number of bits in RGB bit pattern

    // FSM states
    localparam    [1:0] S_start_cycle = 1; // Starting from first LED
    localparam    [1:0] S_rx_rgb = 2; // Get colour bit pattern
    localparam    [1:0] S_get_bit = 3; // process bit from MSB
    localparam    [2:0] S_output_hi = 4; // Set output high
    localparam    [2:0] S_output_low = 5; // Set output low
    localparam    [2:0] S_led_position = 6; // Increment to next LED
    localparam    [2:0] S_reset_delay = 7; // End of 64 string timing

    reg [4:0] t_period_hi_count ; // count 1st half of pulse (max count 25)
    reg [9:0] t_period_low_count ; // count 2nd half of pulse (max count 25)
    reg  CTS ; // Clear to send initially high (ready)
    reg [23:0] data_rx; // store a copy of the incoming data
    reg  data_out ; // data out initially low
    reg [3:0] state, next_state ; // state machine for each step
    reg [6:0] led_pos; // current LED in the string  
    reg [5:0] bit_pos; // current bit position in RGB bit bit_count
    reg  bit_current; // store the current bit value from data_rx
    reg  [5:0] tmp;

    initial begin // initiallise variables at time 0
        CTS = 1'b1;
        data_out = 1'b0;
        next_state = S_start_cycle;
        bit_pos=0;
    end


    assign clearToSend = CTS; // Ready to recieve a data bit when high
    assign serialOut = data_out; // setail data output   


    always @(posedge clk_50ns, posedge reset)
    begin
        if (reset) begin // go to state zero if reset
            CTS = 0;
            data_out = 0;
            next_state = S_start_cycle;
        end


  /***************************************************      
  State machine processing
  ****************************************************/

        else begin
            state = next_state ;
            case (state)
... Various case statements ...

[DRC UCIO-1] Unconstrained Logical Port: 28 out of 28 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: dataIn[23:0], clearToSend, clk_50ns, reset, and serialOut.
 

[zygot]

For constraints files a '#' character starts a comment

Vivado doesn't like having more than 1 timing constraint per input clock pin. Somewhere in the messages is one about over-riding this constraint. For some reason Vivado makes you work to find all of it's IP constraints. Your clk_wiz_0 block put one into your project. You can find it by looking a the IP sources in the project browser window. I personally consider this one of the many bugs introduced into VIvado many many versions ago and preserved for ,er, inscrutable reasons.

Always read all messages, especially the warnings and errors. If you can't figure out what the error source is from an error message ( not uncommon ) then you might be able to do so from previous synthesis messages. When you see that a constraint has been ignored, this is usually due to syntax issues. Vivado occasionally changes constraint syntax from version to version so using older ( or ones that haven't been updated ) master constraints files can cause problems. I'd say that you should use the template feature available in the GUI or by using the -help feature in the TCL console.. but I've had Vivado suggest syntax that is then rejected in subsequent build attempts. Then, it's off to google-land... But be very careful when on the multi-colored brick road; you are likely to run into lot's of out of date references. The Vivado Document Navigator helps sync documentation with your tool version.

But do avail yourself of the built-in help resources for your tool version; most of the time this will get you past the warnings and unexpected consequences of the tools not being able to understand what you are telling them.

What I don't get is why you are using the block diagram IPI flow for such a project. Everything would be much simpler if you just had HDL and constraint files in your project; and you would be able to see what's in the sources... More importantly, many of the Xilinx IP works differently or has a different set of options for the IPI version as opposed to the HDL version. Xilinx has always pushed the IPI design flow, I'm thinking that this is because restricting user's design options is thought to ease support costs. Making users dependent on the FPGA vendor to make important decisions for their designs are certainly better for the bottom line.

Vivado works in mysterious ways.

A simple way to avoid tool version dependencies would be to put the tool version that the source file was made for in the source file. It would be nice if FPGA vendors followed basic software development documentation practices in their sources, especially, for constraints which do not have fixed syntax through tool version timelines.

Edited February 11, 2022 by zygot

[JColvin]

Hi @Guru Tim,

Zygot is correct in that a syntax issue is plaguing your errors regarding the "unconstrained logical port" you are getting from Vivado. I also agree that an all HDL flow would be better for your application.

As a Digilent employee, I feel obligated to point out that in addition to the many available resources through Document Navigator and online in general, you can find one such example design from Digilent with a couple of modules as well as using Xilinx's clocking wizard on our GitHub here: https://github.com/Digilent/Pmod-I2S2.

Thanks,
JColvin

[Guru Tim]

I just looked at this post and had excluded a pin in the above that is in my constraints as I am not currenlty using it.

set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33     } [get_ports { WS2812_data }]; #IO_L15P_T2_DQS_13 Sch=jb_p[1]

After commenting it out, I am still getting the same error

I also have warnings as below. I have changed the name of the clock in the IP Block to sysclk

[Richm]

what is the first create_clock warning about? I don't think you need or want to use this in combination with the clocking wizard. Also sysclk != sys_clk.

If you click on the board tab does it show a clock source? If so, you can right click the clock source and add it to block design. This will add the input pin(s) and a clocking wizard and all the necessary constraints.

I'm no tcl expert, but I separate the pin constraints into 2 lines ( for a ZCU104 ) :

set_property IOSTANDARD LVCMOS33 [get_ports led0]
set_property PACKAGE_PIN D5 [get_ports led0]

note no ';' termination or curlies

[elodg]

The warnings mean the get_ports command is not returning any objects. Also, your block design does not have 28 ports. Check the top-level vhd wrapper of the block design for correct ports and their names.