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Workable project Microblaze+DDR3 for Arty S7


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Hi guys,

Please help to get  Arty S7  up  within Microblaze  + DDR3  working together. I've spent a couple  weeks to built right configuration where Microblaze that has  access to DDR3  -  I ve tried numerois  examples  including in Digilent  ones  that bit oldy - but no results. Currently I'm  using vivado 2020.2    I managed to built stable Microblaze configuration using directly  ddr_clk  or sys clock but when I 'm trying to use 'ui_clk' of MIG7 as source clock for Microblaze  and the rest  of design -  everithing goes wrong - Vitis says  that Microblaze is held in reset.       Has anyone managed to get   working the project  with Microblaze  + DDR3  working together for Vivado 2020? Any links.. Thanks in advance


Edited by westman
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Hi @westman

The DDR Clock pin is intended to be connected to the MIG's sys_clk_i input. The MIG preset also is configured such that ui_addn_clk_0 is (near enough to) 200 MHz and can be used to drive ref_clk_i. The rest of the Microblaze design should be driven by the MIG's ui_clk or another clock derived from it. There's also a current issue that prevents the sys_clk_i input from being connected to the DDR Clock board interface, where the workaround is to instead manually constrain the port with an XDC file. There are some instructions on wiring the MIG up like this that can be found here: https://reference.digilentinc.com/programmable-logic/guides/microblaze-adding-ddr.

Edit: "Microblaze held in reset" implies to me that the polarity of the reset may be incorrect, please check the IP ports that the reset interface is connected to and make sure they are expecting it to be active low.



Edited by artvvb
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