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Found 7 results

  1. Hi, I have a Microblaze design connected to a UartLite instance running on my Arty S7-25, also running FreeRTOS. I'm running into a problem where occasionally when I receive characters from my PC, the application crashes. I can reliably reproduce the problem if I type characters fast. In my code, I'm echoing back the received character and when return/enter is typed it echos back the entire string received up to that point. It's meant to be a command line interface. Any ideas what I'm doing wrong with the UartLite instance? Code for the thread that does all the UartLite work is attached. debug_uart_thread.c
  2. Or, more specifically, I need the Manufacturer's Part Number for power jack J13. Thanks, Kevin
  3. Hi guys, Please help to get Arty S7 up within Microblaze + DDR3 working together. I've spent a couple weeks to built right configuration where Microblaze that has access to DDR3 - I ve tried numerois examples including in Digilent ones that bit oldy - but no results. Currently I'm using vivado 2020.2 I managed to built stable Microblaze configuration using directly ddr_clk or sys clock but when I 'm trying to use 'ui_clk' of MIG7 as source clock for Microblaze and the rest of design - everithing goes wrong - Vitis says that Microblaze is held in reset. Has anyone managed to get working the project with Microblaze + DDR3 working together for Vivado 2020? Any links.. Thanks in advance
  4. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[1]}] set_property -dict {PACKAGE_PIN L18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[1]}] set_property -dict {PACKAGE_PIN M14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[0]}] set_property -dict {PACKAGE_PIN N14 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[0]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[2]}] set_property -dict {PACKAGE_PIN M17 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[2]}] set_property -dict {PACKAGE_PIN M18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_p[3]}] set_property -dict {PACKAGE_PIN N18 IOSTANDARD TMDS_33} [get_ports {hdmi_out_n[3]}] This works great on S7. The problem comes in when trying to use my HDMI PMOD with my new Arty A7 board. I looked up the PMOD pins, and got // for the A7: // top row is D12, A11, B11, G13 // bot row is K16, A18, B18, D13 // so TMDS1 is {B11, G13} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {D12, A11} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {B18, D13} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {K16, A18} = {hdmi_out_n[3], hdmi_out_p[3]} and my constraints look like this set_property -dict { PACKAGE_PIN G13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[1] }]; #IO_0_15 Sch=ja[1] set_property -dict { PACKAGE_PIN B11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[1] }]; #IO_L4P_T0_15 Sch=ja[2] set_property -dict { PACKAGE_PIN A11 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[0] }]; #IO_L4N_T0_15 Sch=ja[3] set_property -dict { PACKAGE_PIN D12 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[0] }]; #IO_L6P_T0_15 Sch=ja[4] set_property -dict { PACKAGE_PIN D13 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[2] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] set_property -dict { PACKAGE_PIN B18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[2] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] set_property -dict { PACKAGE_PIN A18 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_p[3] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] set_property -dict { PACKAGE_PIN K16 IOSTANDARD TMDS_33 } [get_ports { hdmi_out_n[3] }]; #IO_25_15 Sch=ja[10] So as far as I can tell, I made sure that the same JA pins map to what the HDMI PMOD expects. All the RTL code is the same. But now I get these errors Not sure if this is one error causing another, or two different errors. First of all, it seems like the PMOD negative and positive pins are somehow swapped. Or at least that's how I am interpreting ”the positive port (P-side) of a differential pair cannot be placed on a negative package pin”. The other mystery is site IOB_X0Y149 not being part of a differential pair. Any help is appreciated, since this is my first foray into worrying about pin polarity
  5. I understand quite a few things have changed with the SDK to Vitis migration on the software side. But, I am having trouble with the hardware also I followed this tutorial and I get two error while trying to generate bitstream https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Any help is greatly appreciated. Thanks in advance The error message is as follows - [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'system.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: system_microblaze_0_0 system_axi_gpio_input_0 system_axi_gpio_led_0 system_mdm_1_0 system_axi_uartlite_0_0 system_axi_quad_spi_0_0 system_axi_smc_0 system_clk_wiz_0_0 system_ilmb_bram_if_cntlr_0 system_axi_timer_0_0 system_microblaze_0_axi_intc_0 system_microblaze_0_axi_periph_0 system_microblaze_0_xlconcat_0 system_mig_7series_0_0 system_rst_clk_wiz_0_100M_0 system_rst_mig_7series_0_81M_0 system_xadc_wiz_0_0 system_dlmb_bram_if_cntlr_0 system_dlmb_v10_0 system_ilmb_v10_0 system_lmb_bram_0 system_xbar_0 [Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]).
  6. xinx_92

    Arty S7 with Simulink

    Hello there, I´m not really new to FPGA because I'm used to program Xilinx FPGAs via System Generator on dSpace platforms. However I'm really new with out-of-the-box FPGA programming. I got myself an ARTY S7 development kit and i figured maybe it's also "easy" to deploy my Simulink models via Systems Generator on These FPGAs. But unfortunately I have no idea where to start. Does someone of you guys have experience with deploying Simulink models out of Vivado System Generator to the ARTY S7 board? Thanks in advance
  7. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
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