I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed.
To achevieve this goal, I designed a self made pcore to act as a clock generator.
This "720p compliant clock generator" pcore is a simple vhdl/mpd file.
Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE.
The idea was to replace the original clock generator of the design with this core.
Instead of delivering 600Mhz and 75MHz outputs, it delivers 594MHz and 74.25MHz.
74.25MHz clock is intended to clock buses, microblaze, hdmi_out core
594MHz clocks are intended to clock MPMC core (8 times microblaze clocks).
Now for my questions ?:
1/ I am not so sure about the locked/rst chains I designed. Could anyone confirm it is correct or give me suggestions on how to make it good ?
2/ I can no longer use the clock wizard in XPS as I replaced the original clock generator with this core. If I try to launch Clock Wizard in XPS, it complains there is no clock generator core and tells me to add one from the IP Library. My question : is there a way I could "persuade" XPS that my core is a clock generator so that it can calculate and validate timings with this home made core ?
3/ Last (but not least) : the project does generate a bitstream. However I'm quite sure the whole timing part is not processed as it does not work. No signal from hdmi_out when using this core. The number of files produced during bitstream generation is awfully low (400 instead of more than 2300 when generating with original design). So I guess I must have missed something : probably the time constraints. The problem is that I have absolutely no idea where to begin with this as I have never ever coded timing constrains..
I would really appreciate any guidance on how to solve these problems. Cheers.
Question
chcollin
Hi,
I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed.
To achevieve this goal, I designed a self made pcore to act as a clock generator.
This "720p compliant clock generator" pcore is a simple vhdl/mpd file.
Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE.
The idea was to replace the original clock generator of the design with this core.
Instead of delivering 600Mhz and 75MHz outputs, it delivers 594MHz and 74.25MHz.
Now for my questions ? :
1/ I am not so sure about the locked/rst chains I designed. Could anyone confirm it is correct or give me suggestions on how to make it good ?
2/ I can no longer use the clock wizard in XPS as I replaced the original clock generator with this core. If I try to launch Clock Wizard in XPS, it complains there is no clock generator core and tells me to add one from the IP Library. My question : is there a way I could "persuade" XPS that my core is a clock generator so that it can calculate and validate timings with this home made core ?
3/ Last (but not least) : the project does generate a bitstream. However I'm quite sure the whole timing part is not processed as it does not work. No signal from hdmi_out when using this core. The number of files produced during bitstream generation is awfully low (400 instead of more than 2300 when generating with original design). So I guess I must have missed something : probably the time constraints. The problem is that I have absolutely no idea where to begin with this as I have never ever coded timing constrains..
I would really appreciate any guidance on how to solve these problems. Cheers.
N.B : this is an XPS project under ISE 14.7.
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