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Found 4 results

  1. Hi, I am trying to follow the HDMI for the Genesys ZU-5EV board as described here: I have and error in the "Launch the Vitis Baremetal Software Application" It looks like a path problem with the "/" and "\", which i guess is also related with the makefiles that the demos is using in 5ev_boot and 5ev_hdmi_demo_system. There is one line which clearly is not in my computer: XPFM_PATH = C:/Users/bvanca/Downloads/Zybo-Z7-20-HDMI-2020.1-1/hw/Genesys-ZU/sw/ws/5ev_hw_pf/export/5ev_hw_pf/5ev_hw_pf.xpfm I have tried to change this path, but i did not fine this file in the folder of the demo. I have also changed the path of the lscript.ld as i realize that was also wrong and after clean and build again i still have error, but this time there is almost no information. It seems that there is still an error in the make file After that i have tried to run the application and i get the following messages in the Tera Any idea on how to change the make files? should it work directly in the Genesys ZU-5EV board? Many thanks in advance Victor
  2. I have problems with HDMI demo on ZYBO Z7-20, The demo runs well but the resolutions are not correct its kind of crops the stream, the other problem is that on photos and videos red lines appear on edges of the objects and gradients, this happens on videos and photos and not on text, for example if I watch a youtube most of corners of objects get this red lines and other texts for example video description looks normal
  3. Hi, I'm trying to tune Atlys HDMI Demo project so that HDMI output delivers a pure 74.25 MHz 720p signal and not 75 MHz as actually designed. To achevieve this goal, I designed a self made pcore to act as a clock generator. This "720p compliant clock generator" pcore is a simple vhdl/mpd file. Attached is a diagram of what this pcore does. Mainly it is supposedly using one sole CMT, implementing cascading two DCM_CLKGEN and one PLL_BASE. The idea was to replace the original clock generator of the design with this core. Instead of delivering 600Mhz and 75MHz outputs, it delivers 594MHz and 74.25MHz. 74.25MHz clock is intended to clock buses, microblaze, hdmi_out core 594MHz clocks are intended to clock MPMC core (8 times microblaze clocks). Now for my questions ? : 1/ I am not so sure about the locked/rst chains I designed. Could anyone confirm it is correct or give me suggestions on how to make it good ? 2/ I can no longer use the clock wizard in XPS as I replaced the original clock generator with this core. If I try to launch Clock Wizard in XPS, it complains there is no clock generator core and tells me to add one from the IP Library. My question : is there a way I could "persuade" XPS that my core is a clock generator so that it can calculate and validate timings with this home made core ? 3/ Last (but not least) : the project does generate a bitstream. However I'm quite sure the whole timing part is not processed as it does not work. No signal from hdmi_out when using this core. The number of files produced during bitstream generation is awfully low (400 instead of more than 2300 when generating with original design). So I guess I must have missed something : probably the time constraints. The problem is that I have absolutely no idea where to begin with this as I have never ever coded timing constrains.. I would really appreciate any guidance on how to solve these problems. Cheers. N.B : this is an XPS project under ISE 14.7.
  4. I'm following along with the instruction provided on the GitHub ( to test the functionality of the Zybo board's HDMI ports. I followed the instruction to the T but cannot seem to get a signal to pass through. At first, I connected my cable box to the HDMI Rx and then I switched to my laptop. In both instances, not only did my TV monitor not detect a signal, but the output on the sdk terminal was that the HDMI-in was unplugged (see first attached photo). The HDP / LD9 LED near the HDMI port turns on, telling me it is detecting a signal. Using the Zybo-Z7 reference manual, I deduced that it might be due to an issue with resolution, but if I try to change the resolution, I get 'stuck' in that menu (see second attached photo) and have to restart the processes by clicking run-as -> Launch on Hardware. I also notice the clock frequency is set to 0, but I'm not exactly sure what could be the issue. I have also attached the block design and xdc file as I'm assuming the issue could be there since the pixel clock isn't running. design_1.pdf Zybo-Z7-Master.xdc