Norbert96 Posted October 14, 2020 Share Posted October 14, 2020 Hi! I have been working on a digital filter in LabVIEW for and ADC called AD7402. Can somebody explain the following codesequence? I don't understand what it does. I can find all the code in the datasheet of the ADC in the attachments. WORD_CLK = output word rate */ always @ (negedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; end 16'd256:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end 16'd512:begin DATA <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; end 16'd1024:begin DATA <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; end 16'd2048:begin DATA <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; end 16'd4096:begin DATA <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; end default:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end endcase end AD7402.pdf Link to comment Share on other sites More sharing options...
JColvin Posted October 16, 2020 Share Posted October 16, 2020 Hi @Norbert96, Well, based on the comment in the code and briefly looking at the datasheet, I would think that is their chosen Verilog implementation of how they are taking the output of the sinc filter at different decimation rates, with the bitsize of the output increasing as the decimation rate increased. This is explained a bit more on the previous page of the datasheet to where you found this code snippet. Thanks, JColvin Link to comment Share on other sites More sharing options...
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Norbert96
Hi!
I have been working on a digital filter in LabVIEW for and ADC called AD7402.
Can somebody explain the following codesequence? I don't understand what it does.
I can find all the code in the datasheet of the ADC in the attachments.
WORD_CLK = output word rate */
always @ (negedge word_clk )
begin
case ( dec_rate )
16'd32:begin
DATA <= (diff3[15:0] ==
16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
end
16'd64:begin
DATA <= (diff3[18:2] ==
17'h10000) ? 16'hFFFF : diff3[17:2];
end
16'd128:begin
DATA <= (diff3[21:5] ==
17'h10000) ? 16'hFFFF : diff3[20:5];
end
16'd256:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
16'd512:begin
DATA <= (diff3[27:11] ==
17'h10000) ? 16'hFFFF : diff3[26:11];
end
16'd1024:begin
DATA <= (diff3[30:14] ==
17'h10000) ? 16'hFFFF : diff3[29:14];
end
16'd2048:begin
DATA <= (diff3[33:17] ==
17'h10000) ? 16'hFFFF : diff3[32:17];
end
16'd4096:begin
DATA <= (diff3[36:20] ==
17'h10000) ? 16'hFFFF : diff3[35:20];
end
default:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
endcase
end
AD7402.pdf
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