Arty_Z7_20_wrapper project???

[lurk101]

I've given up on working with the Arty Z7-20 with 20.1 and reverted to Vivado 19.1 and the 19.1 SoCSDK. Using petalinux tools and Petalinux-Arty-Z7-20 project I've been able to create a bootable Linux SD image. So far so good! My objective is to port a project adding AXI slave IP, Linux drivers and applications.

The aforementioned project contains a Petalinux-Arty-Z7-20-2017.4-1.bsp file which in turn contains the projects matching Arty_Z7_20_wrapper.bit IP. This project seems like a good starting point for what I need, but where can I find the correct project used to generate Arty_Z7_20_wrapper.bit so that I can insert my IP?

[chaitusvk]

Rather than using the BSP's you have to create your own hard ware ...

use petalinux-config --get-hw-description=<PATH TO design_1_wrapper_hw_platform_0>

I wish the following videos sloves your problem

 

[lurk101]

Thanks. That is a long, detailed video... precisely the thing I was hoping to avoid. It's too bad the documentation and support material for the Arty Z7 is so scant and outdated. The project linked at Digilent's Arty Z7 page builds a complete bootable Linux image and would provide a good starting point to add a single IP block, Linux driver, and application. All of the pieces are there except for how to reproduce the critical .bit file.

[JColvin]

Hi @lurk101,

I believe the base design the Petalinux Material is based off of is available here: https://github.com/Digilent/Arty-Z7-20-base-linux, which should let you generate the bitstream. I haven't tried this with this particular project myself, but the general flow on how to get that style of project up and running (Digilent has transitioned to different styles of project recreation) is detailed here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start.

Thanks,
JColvin