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Found 3 results

  1. Hello, I hope you will be enjoying your vacations if you have been given some. For me this has meant finally being able to work on my spare-time experiment and finally reach closure on my upgraded design. Let me describe the process. The ArtyZ7-20 is just the initial prototyping. I'm going to move to real production FPGA boards ASAP (probably in August) but for the time being I'd just want to go ahead with the Arty. The system is systemverilog RTL and barebone C++. The initial design was 100Mhz and 6-stage pipe. Vivado estimated about 2.2W power. I suspect it was much lower than that. I ran it over USB2. Let me be clear my mainboard has a fairly beefy usb2 going beyond usual specification. I later went ahead with a 12-stage pipeline. I was unable to run it on USB2, but it runs rock stable on USB3. In the last few weeks I've upgraded it to 200Mhz. Vivado now estimates 5.5W. I never expected this to be able to run on USB3 power (I haven't tried, but I doubt my USB3 can deliver 1A) so I've hooked the ARTY through its power jack to a industrial supply (details, if needed, in a later message) The board gives up. If I leave the board free-running, it hangs almost instantly. Here's how it goes by stepping it in the debugger: Booting ok, DHCP fails (ok) and fixed ip is estabilished. Server correctly found, input requested and correctly received. Input feed to PL PL start As soon as I pass beyond the {4} breakpoint, the card hangs. The debugger will never hit the next breakpoint. I can tell the thing is more relevant than just software because my PL turns on red LD5 when idle. It would turn on green and eventually blue plus animate LD0-3. This never happens. I was thinking about hooking a bunch of capacitors to the supply and see if it improves but I guess there might be other issues to consider as well. Do you have any suggestion?
  2. Hello, I am new to FPGAs. Recently I bought a ARTY Z7. I wrote basic verilog code and programmed it it worked fine. Then i wanted to use the QSPI to flash the board so that the configuration gets loaded after poweroff. I tried a lot debugging why it was not working but i have no clue. I also went through lot of similar forum posts and i tried most of them but didnt work yet for me. These are the things i did in short. the program device is working properly only i am having trouble with the flashing QSPI I kept the jumper in JTAG position I have taken Zynq Processing System IP into the design along with the the HDL module and created a HDL wrapper I made fsbl applicatin project in sdk and created the boot image I checked the USB drivers they were ok I was getting this error when i was trying to flash the fpga Looking forward for any help and suggessions, Thanks a lot.
  3. I've given up on working with the Arty Z7-20 with 20.1 and reverted to Vivado 19.1 and the 19.1 SoCSDK. Using petalinux tools and Petalinux-Arty-Z7-20 project I've been able to create a bootable Linux SD image. So far so good! My objective is to port a project adding AXI slave IP, Linux drivers and applications. The aforementioned project contains a Petalinux-Arty-Z7-20-2017.4-1.bsp file which in turn contains the projects matching Arty_Z7_20_wrapper.bit IP. This project seems like a good starting point for what I need, but where can I find the correct project used to generate Arty_Z7_20_wrapper.bit so that I can insert my IP?