So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results.
Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
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Katherine
Hello, (FPGA board is Nexys A7 100T)
So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results.
Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
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